Reduction of thermal conductivity κ while preserving high electrical conductivity σ in materials continues to be a vital goal in thermoelectric study for the reuse of exhaust heat energy. In the use of an eco-friendly and ubiquitous element, Si as thermoelectric material, high κ value in bulk Si is the essential bottleneck to achieve high dimensionless figure of merit. This is a motivation for many recent studies on reducing κ in Si, by nanostructuring, e.g., using grains/wires with size smaller than the phonon mean free path. However, κ reduction that can be achieved tends to be saturated presumably due to an amorphous limit. Here, we present a nanoarchitecture for defeating the κ amorphous limit while preserving bulk-like σ. This new nanoarchitecture is an assembly of Si nanocrystals with oriented crystals separated by a 1-monolayer amorphous layer with well-controlled nanoscale shaped interfaces. At these interfaces, novel phonon scattering occurs resulting in κ reduction below the amorphous limit. Preservation of bulk-like σ results from the coherency of the carrier wavefunctions among the oriented nanocrystals separated by the ultrathin amorphous layer.

Phonon transport in Si films was controlled using epitaxially-grown ultrasmall Ge nanodots (NDs) with ultrahigh density for the purpose of developing Si-based thermoelectric materials. The Si/Ge ND stacked structures, which were formed by the ultrathin SiO2 film technique, exhibited lower thermal conductivities than those of the conventional nanostructured SiGe bulk alloys, despite the stacked structures having a smaller Ge fraction. This came from the large thermal resistance caused by phonon scattering at the Si/Ge ND interfaces. The phonon scattering can be controlled by the Ge ND structure, which was independent of Si layer structure for carrier transport. These results demonstrate the effectiveness of ultrasmall epitaxial Ge NDs as phonon scattering sources, opening up a route for the realisation of Si-based thermoelectric materials.

The high electrical and drastically-low thermal conductivities, a vital goal for high performance thermoelectric (TE) materials, are achieved in Si-based nanoarchitecture composed of Si channel layers and epitaxial Ge nanodots (NDs) with ultrahigh areal density (~1012 cm−2). In this nanoarchitecture, the ultrasmall NDs and Si channel layers play roles of phonon scattering sources and electrical conduction channels, respectively. Electron conductivity in n-type nanoacrhitecture shows high values comparable to those of epitaxial Si films despite the existence of epitaxial NDs. This is because Ge NDs mainly scattered not electrons but phonons selectively, which could be attributed to the small conduction band offset at the epitaxially-grown Si/Ge interface and high transmission probability through stacking faults. These results demonstrate an independent control of thermal and electrical conduction for phonon-glass electron-crystal TE materials by nanostructure designing and the energetic and structural interface control.

Half-Heusler compounds TiCoSb, ZrCoSb, HfCoSb were prepared by a spark plasma sintering (SPS) technique. Their thermoelectric and thermophysical properties were measured. The band gap energy estimated from the electrical resistivity becomes small in the following order: TiCoSb (0.16 and 0.40 eV), ZrCoSb (0.14 eV), HfCoSb (0.07 eV). The largest thermoelectric power is obtained as -304 µV/K at 641 K for TiCoSb. The thermal conductivity and Debye temperature become small in the following order: TiCoSb, ZrCoSb, HfCoSb. The contribution to the thermal conductivity is mainly due to the lattice contribution. The maximum value of ZT is 0.020 at 986 K for ZrCoSb. IntroductionThe thermoelectric performance of a material at a given temperature is given as the dimensionless figure of merit ZT =

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Wafer bonding is an attractive process to creat new structures and materials, alternative to conventional bulk-Si substrates, in the form of substrates for the advanced metal-oxide-semiconductor field effect transistors (MOSFETs). A germanium on insulator (GOI) substrate attracts much attention because it makes the best use of the higher carrier mobility advantages compared with Si, and is suitable to further downscaling of Ge MOSFET dimensions. However, careful consideration is given especially to the bonded interface between Ge and buried oxide, which should have a device grade quality. In this work, we fabricate GOI substrates by using a wafer bonding method. Atomic structures, chemistry, and electrical properties of the Ge/BOX interface are also characterized.