In this project, an innovative design of energy efficient Vedic Multiplier using a prehistoric Vedic mathematics method known as "Anurupyena Shunyamanyat" have been implemented on FPGA. Anurupyena Shunyamanyat is a Sanskrit name which in simple words means ' proportionality 'or ' similarly '. This Sutra is highly useful to find products of two numbers when both of them are near the frequent bases like 10, 50, 500 etc (multiples of powers of 10). Lesser time and energy efficient is today's world demand. Choice of IO Standard plays a very important role in power indulgence design. So, we have selected most energy efficient IO standard Low Voltage Complementary Metal Oxide Semiconductor also called LVCMOS. Then, we try to achieve more energy efficiency with different technology (40nm and 28nm) based FPGA. Virtex-6 and Kintex-7 are the platforms which have been used in this project. In our paper we have implemented our code on Xilinx ISE Design Suite 14.2 were tested on 28nm and 40nm FPGA. In this project we have observed approx 87-88% decrease in leakage power dissipation when we shift from 40nm to 28nm technology based FPGA.
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