As the feature sizes of devices decrease to the nanoscale, electron microscopy and lithography will become increasingly essential techniques for fabrication and inspection. In this study, we probed the memory effects of MoS2 field-effect transistors (FETs) subjected to electron beam (e-beam) irradiation; after fabricating the devices on 300 nm SiO2/Si substrates, we irradiated the MoS2 FETs with various doses of irradiation from a 30 kV e-beam. The threshold voltage shifted to the negative side and the mobility increased-a so-called memory effect-upon increasing the e-beam dose. These changes resulted from positively charged oxide traps, formed upon e-beam irradiation, in the gate oxide layer. Interestingly, the electrical characteristics of the MoS2 FETs after e-beam irradiation continued to change upon aging: the threshold voltage shifted toward the positive side and the mobility decreased, suggesting that the dominant mechanism changed from the presence of positively charged oxide traps to the presence of negatively charged interface traps. Notably, the threshold voltage shifts of the MoS2 FETs could be retained for one or two days. This behavior should be useful for preparing property-adjustable nanodevices, with particular potential for applications in multi-level memory devices.
Background and aims Ketamine has become a new recreational drug of choice among young people in parts of Asia.Using national databases in Taiwan, this study aimed to (1) examine the yearly trend in the ketamine offence rate over time; (2) estimate the 3-year risk of drug-related re-offence and its correlates among the first-time offenders; and (3) estimate the 3-year standardized mortality ratio (SMR) among the first-time offenders. Design, Setting and Participants Retrospective cohort studies of offenders for recreational ketamine use in a penalty system initiated in 2009. Offenders for recreational ketamine use were identified from the Administrative Penalty System for Schedule III/IV Substances database from 2009 to 2017, and the re-offence rate and mortality among first-time offenders were assessed via record-linkage within the database as well as with both the criminal drug offence database and the national mortality database. The cohort from 2009 to 2016 (n = 39 178) was used for the recidivism analysis and the cohort from 2009 to 2013 (n = 25 357) was used for the 3-year SMR analysis. Measurements Recidivism was estimated using survival analysis of the event as re-arrest for using ketamine, more serious illicit drugs (Schedules I/II), or any illicit drugs (ketamine or Schedules I/II). SMRs were estimated for overall and cause-specific death within 3 years after the first offence for ketamine use. Findings The age-standardized rates for both prevalent (1.38 per 1000) and first-time offenders (0.65 per 1000) peaked in 2013 and then decreased steadily. The 3-year risk of re-offence was 33.85% [95% confidence interval (CI) = 33.23-34.47%) for ketamine use and 39.52% (95% CI = 39.00-40.04%) for any illicit drug use. These first-time offenders had an SMR of 4.9 (95% CI = 4.3-5.4) for overall mortality, 2.1 (95% CI = 1.6-2.7) for natural deaths and 7.6 (95% CI = 6.7-8.6) for unnatural deaths. Conclusions Recreational ketamine use in Taiwan appears to lead not only to high risk for drug-related re-offence but also to excess mortality.
Decreasing read cell current (I CELL ) has become a key trend in nonvolatile memory (NVM). This is not only due to device size and V DD scaling while keeping the same threshold voltage (V TH ), but also to the growing spread of the following applications: 1) multiple-level-cell (MLC) [1-2] to achieve smaller area-per-bit; 2) lower-V DD [3] to save power consumption; 3) Logic-process-compatible onetime programming memories (OTP) for embedding into mobile chips. A smaller I CELL leaves the sense amplifiers (SAs) operation vulnerable to 1) bitline (BL) level offset due to noise, bias and load (C BL ) mismatches and 2) V TH variation. As device size and BL-pitch is continually scaled down, the above factors have become major showstopper for SAs. To tolerate these offsets, small-I CELL NVMs suffer from slow read speed or high read fail probability. Thus, a more largely offset tolerant SA is a prerequisite to achieve faster read speeds. In this study, we propose a new offset tolerant current-sampling-based SA (CSB-SA) to achieve 7× faster read speed than previous SAs for sensing small I CELL . A fabricated 90nm 512Kb OTP macro, using the CSB-SA and our CMOS-logiccompatible OTP cell [4], achieves 26ns macro random access time for reading sub-200nA I CELL . Measurements also confirmed that this 90nm CSB-SA could achieve sub-100nA sensing.Many small-I CELL NVMs employ voltage-mode SA (VSA) [2] with a long BL developing time to tolerate SA offset, at the cost of a reduced read speed. Current-mode SA (CSA) achieves faster read speeds than VSA [1]. Cascodecurrent-load or resistive-divider-like CSAs (RD-CSAs) [1], [5], achieve sub100nA sensing, but require long BL settling times to achieve high-accuracy 1 ststage voltage difference. The inverter-offset-compensated SA (IOC-SA) [6] reduces the SA offset. However, BL offset and BL settling time still limits its advantages with regard to VSA/CSA. In comparison with I CELL and a referencecurrent (I REF ), current-mirror CSA (CM-CSA) [7], has fast read speeds but cannot sense small I CELL due to its input-stage V TH mismatch. Figure 11.5.1 compares the concepts of CSB-SA with previous SAs. CSB-SA uses the same MOS device for current sampling and current-ratio amplifying. This enables V THindependent current sampling schemes for its differential I CELL and I REF inputs. This is significantly different from CM-CSA, using different MOS devices for current-mirroring or I-V conveying, which results in increased vulnerability to V THmismatch. In addition, CSB-SA uses sampled current to generate fast 1 st -stage voltage difference at its BL-decoupled small-load internal nodes. Unlike VSA or RD-CSA, which have to develop their 1 st -stage voltage on the heavy-load BL using continuous I CELL driving. IOC alleviates SA V TH -mismatch but with a complex multi-step V TH -nulling process and numerous switching devices. IOC also does not cancel the SA offset due to transistor width/length or T OX variations, and is still vulnerable to BL noise/C BL mismatch. In our CSB-SA, the sampled currents a...
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