We have previously shown that healthy subjects can transfer coordination skills to the unpracticed hand by performing a unimanual task with the other hand and visualizing a bimanual action using a game-like interactive system. However, whether this system could be used to transfer coordination skills to the paretic hand after stroke and its underlying neural mechanism remain unknown. Here, using a game-like interactive system for visualization during physical practice in an immersive virtual reality environment, we examined coordination skill improvement in the unpracticed/paretic hand after training in 10 healthy subjects and 13 chronic and sub-acute stroke patients. The bimanual movement task was defined as simultaneously drawing non-symmetric threesided squares (e.g., U and C), while the training strategy was performing a unimanual task with the right/nonparetic hand and visualizing a bimanual action. We found large decreases in the intra-hand temporal and spatial measures for movement in the unpracticed/paretic hand after training. Furthermore, a substantial reduction in the inter-hand temporal and spatial interference was observed after training. Additionally, we examined the related cortical network evolution using EEG in both the healthy subjects and stroke patients. Our studies show that the cortical network became more efficient after training in the healthy subjects and stroke patients. These results demonstrate that our proposed method could contribute to the transference of coordination skill to the paretic/unpracticed hand by promoting the efficiency of cortical networks.
Antifuse FPGA because for its low power consumption, high reliability, high security, etc., are widely used in space electronic systems. However, antifuse FPGA running in the space environment is also vulnerable to space radiation. This paper analyzes the single event effects in antifuse FPGA in detail and put forward the TMR and EDAC anti-SEE hardening design and implementation methods. The ground heavy ions accelerated test is conducted to verify the design of hardening; test results and analysis show that the hardening design method can effectively improve the COTS antifuse FPGA for space applications reliability.
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