The limited connectivity of current and next-generation quantum annealers motivates the need for efficient graph minor embedding methods. These methods allow non-native problems to be adapted to the target annealer's architecture. The overhead of the widely used heuristic techniques is quickly proving to be a significant bottleneck for solving real-world applications. To alleviate this difficulty, we propose a systematic and deterministic embedding method, exploiting the structures of both the specific problem and the quantum annealer. We focus on the specific case of the Cartesian product of two complete graphs, a regular structure that occurs in many problems. We decompose the embedding problem by first embedding one of the factors of the Cartesian product in a repeatable pattern. The resulting simplified problem consists in the placement and connecting together of these copies to reach a valid solution. Aside from the obvious advantage of a systematic and deterministic approach with respect to speed and efficiency, the embeddings produced are easily scaled for larger processors and show desirable properties for the number of qubits used and the chain length distribution. We conclude by briefly addressing the problem of circumventing inoperable qubits by presenting possible extensions of our method.

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This study investigates the problem of communication for a network composed of two half-duplex parallel relays with additive white Gaussian noise. Two protocols, i.e., Simultaneous and Successive relaying, associated with two possible relay orderings are proposed. The simultaneous relaying protocol is based on Dynamic Decode and Forward (DDF) scheme. For the successive relaying protocol: (i) a Non-Cooperative scheme based on the Dirty Paper Coding (DPC), and (ii) a Cooperative scheme based on the Block Markov Encoding (BME) are considered. Furthermore, the composite scheme of employing BME at one relay and DPC at another always achieves a better rate when compared to the Cooperative scheme. A "Simultaneous-Successive Relaying based on Dirty paper coding scheme" (SSRD) is also proposed. The optimum ordering of the relays and hence the capacity of the half-duplex Gaussian parallel relay channel in the low and high signal-to-noise ratio (SNR) scenarios is derived. In the low SNR scenario, it is revealed that under certain conditions for the channel coefficients, the ratio of the achievable rate of the simultaneous relaying based on DDF to the cut-set bound tends to be 1. On the other hand, as SNR goes to infinity, it is proved that successive relaying, based on the DPC, asymptotically achieves the capacity of the network.

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Neural architecture search automates neural network design and has achieved state-of-the-art results in many deep learning applications. While recent literature has focused on designing networks to maximize accuracy, little work has been conducted to understand the compatibility of architecture design spaces to varying hardware. In this paper, we analyze the neural blocks used to build Once-for-All (MobileNetV3), ProxylessNAS and ResNet families, in order to understand their predictive power and inference latency on various devices, including Huawei Kirin 9000 NPU, RTX 2080 Ti, AMD Threadripper 2990WX, and Samsung Note10. We introduce a methodology to quantify the friendliness of neural blocks to hardware and the impact of their placement in a macro network on overall network performance via only end-to-end measurements. Based on extensive profiling results, we derive design insights and apply them to hardware-specific search space reduction. We show that searching in the reduced search space generates better accuracylatency Pareto frontiers than searching in the original search spaces, customizing architecture search according to the hardware. Moreover, insights derived from measurements lead to notably higher ImageNet top-1 scores on all search spaces investigated.

Recent developments in Neural Architecture Search (NAS) resort to training the supernet of a predefined search space with weight sharing to speed up architecture evaluation. These include random search schemes, as well as various schemes based on optimization or reinforcement learning, in particular policy gradient, that aim to optimize a parametric architecture distribution and the shared model weights simultaneously. In this paper, we focus on efficiently exploring the important region of a neural architecture search space with reinforcement learning. We propose Deep Deterministic Architecture Sampling (DDAS) based on deep deterministic policy gradient and the actor-critic framework, to selectively sample important architectures in the supernet for training. Through balancing exploitation and exploration, DDAS is designed to combat the disadvantages of prior random supernet warm-up schemes and optimization schemes. Gradient-based NAS approaches require the execution of multiple short experiments in order to combat the random stochastic nature of gradient descent, while still only producing a single architecture. Contrary to this approach, DDAS employs a reinforcement learning-based agent and focuses on discovering a Pareto frontier containing many architectures over the course of a single experiment requiring 1 GPU day. Experimental results for CIFAR-10 and CIFAR-100 on the DARTS search space show that, DDAS can depict in a single search, the accuracy-FLOPs (or model size) Pareto frontier, which outperforms random sampling and search. With a test accuracy of 97.27%, the best architecture found on CIFAR-10 outperforms the original second-order DARTS while using 600M fewer parameters. Additionally, DDAS finds an architecture capable of achieving 82.00% test accuracy on CIFAR-100 while using only 3.14M parameters and outperforming GDAS.

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