The combination of a neuromorphic architecture and photonic computing may open up a new era for computational systems owing to the possibility of attaining high bandwidths and the low-computation-power requirements. Here, the demonstration of photonic neuromorphic devices based on amorphous oxide semiconductors (AOSs) that mimic major synaptic functions, such as short-term memory/long-term memory, spike-timing-dependent plasticity, and neural facilitation, is reported. The synaptic functions are successfully emulated using the inherent persistent photoconductivity (PPC) characteristic of AOSs. Systematic analysis of the dynamics of photogenerated carriers for various AOSs is carried out to understand the fundamental mechanisms underlying the photoinduced carrier-generation and relaxation behaviors, and to search for a proper channel material for photonic neuromorphic devices. It is found that the activation energy for the neutralization of ionized oxygen vacancies has a significant influence on the photocarrier-generation and time-variant recovery behaviors of AOSs, affecting the PPC behavior.

A new strategy is reported to achieve high-mobility, low-off-current, and operationally stable solution-processable metal-oxide thin-film transistors (TFTs) using a corrugated heterojunction channel structure. The corrugated heterojunction channel, having alternating thin-indium-tin-zinc-oxide (ITZO)/indium-gallium-zinc-oxide (IGZO) and thick-ITZO/IGZO film regions, enables the accumulated electron concentration to be tuned in the TFT off- and on-states via charge modulation at the vertical regions of the heterojunction. The ITZO/IGZO TFTs with optimized corrugated structure exhibit a maximum field-effect mobility >50 cm V s with an on/off current ratio of >10 and good operational stability (threshold voltage shift <1 V for a positive-gate-bias stress of 10 ks, without passivation). To exploit the underlying conduction mechanism of the corrugated heterojunction TFTs, a physical model is implemented by using a variety of chemical, structural, and electrical characterization tools and Technology Computer-Aided Design simulations. The physical model reveals that efficient charge manipulation is possible via the corrugated structure, by inducing an extremely high carrier concentration at the nanoscale vertical channel regions, enabling low off-currents and high on-currents depending on the applied gate bias.

Ultrasensitive room-temperature operable gas sensors utilizing the photocatalytic activity of Na-doped p-type ZnO (Na:ZnO) nanoflowers (NFs) are demonstrated as a promising candidate for diabetes detection. The flowerlike Na:ZnO nanoparticles possessing ultrathin hierarchical nanosheets were synthesized by a facile solution route at a low processing temperature of 40 °C. It was found that the Na element acting as a p-type dopant was successfully incorporated in the ZnO lattice. On the basis of the synthesized p-type Na:ZnO NFs, room-temperature operable chemiresistive-type gas sensors were realized, activated by ultraviolet (UV) illumination. The Na:ZnO NF gas sensors exhibited high gas response (S of 3.35) and fast response time (∼18 s) and recovery time (∼63 s) to acetone gas (100 ppm, UV intensity of 5 mW cm), and furthermore, subppm level (0.2 ppm) detection was achieved at room temperature, which enables the diagnosis of various diseases including diabetes from exhaled breath.

In this paper, we demonstrate high mobility solution-processed metal-oxide thin-film transistors (TFTs) by using a high-frequency-stable ionic-type hybrid gate dielectric (HGD). The HGD gate dielectric, a blend of sol-gel aluminum oxide (AlOx) and poly(4-vinylphenol) (PVP), exhibited high dielectric constant (ε~8.15) and high-frequency-stable characteristics (1 MHz). Using the ionic-type HGD as a gate dielectric layer, an minimal electron-double-layer (EDL) can be formed at the gate dielectric/InOx interface, enhancing the field-effect mobility of the TFTs. Particularly, using the ionic-type HGD gate dielectrics annealed at 350 °C, InOx TFTs having an average field-effect mobility of 16.1 cm2/Vs were achieved (maximum mobility of 24 cm2/Vs). Furthermore, the ionic-type HGD gate dielectrics can be processed at a low temperature of 150 °C, which may enable their applications in low-thermal-budget plastic and elastomeric substrates. In addition, we systematically studied the operational stability of the InOx TFTs using the HGD gate dielectric, and it was observed that the HGD gate dielectric effectively suppressed the negative threshold voltage shift during the negative-illumination-bias stress possibly owing to the recombination of hole carriers injected in the gate dielectric with the negatively charged ionic species in the HGD gate dielectric.

In this study, we fabricated an array of all-inkjet-printed vertical Schottky barrier (SB) transistors and various logic gates on a large-area substrate. All of the electronic components, including the indium−gallium−zinc−oxide (IGZO) semiconductor, reduced graphene oxide (rGO), and indium−tin−oxide (ITO) electrodes, and the ion-gel gate dielectric, were directly and uniformly printed onto a 4 in. wafer. The vertical SB transistors had a vertically stacked structure, with the inkjet-printed IGZO semiconductor layer placed between the rGO source electrode and the ITO drain electrode. The ion-gel gate dielectric was also inkjet-printed in a coplanar gate geometry. The channel current was controlled by adjusting the SB height at the rGO/IGZO heterojunction under application of an external gate voltage. The high intrinsic capacitance of the ion-gel gate dielectric facilitated modulation of the SB height at the source/channel heterojunction to around 0.5 eV at a gate voltage lower than 2 V. The resulting vertical SB transistors exhibited a high current density of 2.0 A•cm −2 , a high on−off current ratio of 10 6 , and excellent operational and environmental stabilities. The simple device structure of the vertical SB transistors was beneficial for the fabrication of all-inkjet-printed low-power logic circuits such as the NOT, NAND, and NOR gates on a large-area substrate.