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Ni-rich layered LiNi 0.84 Co 0.10 Mn 0.06 O 2 cathode material was modified by doping with vanadium to enhance the electrochemical performances. The XRD, FESEM and XPS analyses were indicated that the vanadium is successfully doped in the crystal lattice of LiNi 0.84 Co 0.10 Mn 0.06 O 2 with high crystallinity. 0.05 mol% vanadium doped LiNi 0.84 Co 0.10 Mn 0.06 O 2 exhibits superior initial discharge capacity of 204.4 mAh g −1 , cycling retention of 88.1% after 80 cycles and rate capability of 86.2% at 2 C compared to those of pristine sample. It can be inferred that the vanadium doping can stabilize the crystal structure and improve the lithium-ion kinetics of the layered cathode materials.

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SUMMARYThis paper addresses the map merging problem, which is the most important issue in multi-robot simultaneous localization and mapping (SLAM) using the Rao–Blackwellized particle filter (RBPF-SLAM) with unknown initial poses. The map merging is performed using the map transformation matrix and the pair of map merging bases (MMBs) of the robots. However, it is difficult to find appropriate MMBs because each robot pose is estimated under multi-hypothesis in the RBPF-SLAM. In this paper, probabilistic map merging (PMM) using the Gaussian process is proposed to solve the problem. The performance of PMM was verified by reducing errors in the merged map with computer simulations and real experiments.

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Structural advancements of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) without punch-through-stopper (PTS) were introduced using fully calibrated TCAD for the first time. It is challenging to scale down conventional bulk FinFETs into 5-nm technology node due to the sub-fin leakage increase. Meanwhile, bottom oxide deposition after anisotropic etching for source/drain (S/D) epi formation prevents the sub-fin leakage effectively even without the PTS doping, thus achieving better gate-to-channel controllability. Bottom oxide FinFETs also have smaller gate capacitances than do conventional FinFETs because the parasitic capacitances decrease by smaller S/D epi separated from the bottom Si layer, which reduces junction and outer-fringing capacitances. But smaller S/D epi decreases the stresses along the channel direction, and the effective widths decrease by the bottom oxide layer blocking the current paths at the bottom side of fin channels. Furthermore, increase of the interconnect resistance and capacitance parasitics down to 5-nm node diminishes the improvements of total delays as the interconnect wire length increases greatly. In spite of these drawbacks, 5-nm node bottom oxide FinFETs achieve smaller total delays than do the 7-nm node conventional FinFETs, especially for low-power applications, thus promising for the scalability of bulk FinFETs along with simple and reliable process by avoiding PTS step.INDEX TERMS 5-nm node, bottom oxide, FinFETs, punch-through-stopper (PTS), intrinsic delay, total delay, sub-fin leakage.

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