Face recognition (FR) and license plate recognition (LPR) are very crucial algorithms for identification of humans and vehicles in several applications such as surveillance, traffic and access-control. The advances in small singleboard computers with high parallel processing power capabilities and the use of low-power Neural Processing Units (NPU) inside embedded System on Chips (SoC), enable real-time face detection (FD) and LPR at the edge. On the other hand, it is still a challenge to run multiple algorithms concurrently with high accuracy and prompt execution (high frame rates) that requires a very efficient software/video analytics algorithm development. Both FR and LPR algorithms need two-stage processing that involve detection and recognition. In this study, we propose a method that enables simultaneous face detection associated with landmark and quality information and LPR at the edge. The FD pipeline detects and tracks the faces, extracts landmarks and quality of faces, to select appropriate faces for recognition and then sends them to face recognition server. LPR algorithm consecutively performs detection and recognition on the embedded platform. Extended YOLO model is utilized for face selection while pruned YOLO and LPRNet models are exploited for license plate detection and license plate reading, respectively. In order to enable real-time performance with high accuracy; optimized AI-models and software architecture are used. As a result of this study, we obtain a high-performance, high-precision and real-time combined face/LPR recognition system which can be very useful for surveillance and security applications.
In recent years, number of edge computing devices and artificial intelligence applications on them have advanced excessively. In edge computing, decision making processes and computations are moved from servers to edge devices. Hence, cheap and low power devices are required. FPGAs are very low power, inclined to do parallel operations and deeply suitable devices for running Convolutional Neural Networks (CNN) which are the fundamental unit of an artificial intelligence application. Face detection on surveillance systems is the most expected application on the security market. In this work, TinyYolov3 architecture is redesigned and deployed for face detection. It is a CNN based object detection method and developed for embedded systems. PYNQ-Z2 is selected as a target board which has low-end Xilinx Zynq 7020 System-on-Chip (SoC) on it. Redesigned TinyYolov3 model is defined in numerous bit width precisions with Brevitas library which brings fundamental CNN layers and activations in integer quantized form. Then, the model is trained in a quantized structure with WiderFace dataset. In order to decrease latency and power consumption, onchip memory of the FPGA is configured as a storage of whole network parameters and the last activation function is modified as rescaled HardTanh instead of Sigmoid. Also, high degree of parallelism is applied to logical resources of the FPGA. The model is converted to an HLS (High-Level-Synthesis) based application with using FINN framework and FINN-HLS library which includes the layer definitions in C++. Later, the model is synthesized and deployed. CPU of the SoC is employed with multithreading mechanism and responsible for preprocessing, postprocessing and TCP/IP streaming operations. Consequently, 2.4 Watt total board power consumption, 18 Frames-Per-Second (FPS) throughput and 0.757 Mean-Average-Precision (mAP) accuracy rate on Easy category of the WiderFace are achieved with 4 bits precision model.
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