Room‐temperature, solution‐processed, silicon nanoparticle thin films show significant gating with distinct hysteresis in their current–voltage characteristics. Device performance strongly depends on measurement environment and charge transport is determined by particle surfaces. Particle encapsulation with polymethyl methacrylate or Al2O3 reduces hysteresis and device sensitivity against environmental influences. Both Al2O3 coating and UV exposure during measurements alter current transport and enhance conductivity, providing evidence for surface‐dominated transport.

Novel graded carbon aerogels were synthesized to study the impact of different synthesis parameters on the material properties on a single sample and to test a new, locally resolved thermal conductivity measurement technique. Two identical cylindrical aerogels with a graded structure along the main cylindrical axis were synthesized. Along the gradient with an extension of about 20 mm the densities range from 240 to 370 kg·m -3 and the effective pore diameter determined via small angle X-ray scattering and SEM increase systematically from 70 up to 11000 nm. One specimen was cut perpendicular to the cylinder axis into disc shaped samples; their thermal conductivities in argon atmosphere as determined via standard laser flash range from 0.06 to 0.12 W·m -1 ·K -1 at 600°C. The second specimen, cut to obtain a sample with the gradient in plane, was investigated with a spatially resolved laser flash technique at ambient conditions. The results of the two different techniques are compared and discussed in detail.

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Nanoparticles exhibit a decrease in sintering and melting temperature with decreasing particle size in comparison to the corresponding bulk material. After melting or sintering of the nanoparticles, the material behaves like the bulk material. Therefore, high-strength and temperatureresistant joints can be produced at low temperatures, which is of big interest for various joining tasks. Joints (substrate: Cu) were prepared with an Ag nanoparticle-containing paste. The influence of the adjustable process parameters joining pressure, joining temperature, holding time, heating rate, thickness of paste application, surface treatment, pre-drying process, and subsequent heat treatment on the strength behavior of the joints was investigated. It is shown that in particular, the joining pressure exerts an essential influence on the achievable strengths. In addition, temperature, holding time, and thickness of paste application have a significant effect on strength behavior. In contrast, the pre-drying process, heating rate, surface pre-treatment, and subsequent heat treatment possess hardly any influence on joint strength.

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The high parallelism of future Teradevices, which are going to contain more than 1,000 complex cores on a single die, requests new execution paradigms. Coarse-grained dataflow execution models are able to exploit such parallelism, since they combine side-effect free execution and reduced synchronization overhead. However, the terascale transistor integration of such future chips make them orders of magnitude more vulnerable to voltage fluctuation, radiation, and process variations. This means dynamic fault-tolerance mechanisms have to be an essential part of such future system. In this paper, we present a fault tolerant architecture for a coarse-grained dataflow system, leveraging the inherent features of the dataflow execution model. In detail, we provide methods to dynamically detect and manage permanent, intermittent, and transient faults during runtime. Furthermore, we exploit the dataflow execution model for a thread-level recovery scheme. Our results showed that redundant execution of dataflow threads can efficiently make use of underutilized resources in a multi-core, while the overhead in a fully utilized system stays reasonable. Moreover, thread-level recovery suffered from moderate overhead, even in the case of high fault rates

Cycle-by-cycle lockstep execution as implemented by current embedded processors is unsuitable for heterogeneous multi-cores, because the different cores are not cycle synchronous. Furthermore, current and future safety-critical applications demand fail-operational execution, which requires mechanisms for error recovery. In this paper, we propose a loosely-coupled redundancy approach which combines an in-order with an out-of-order core and utilizes transactional memory for error recovery. The critical program is run in dual-modular redundancy on the out-of-order and the in-order core. The memory accesses of the out-of-order core are used to prefetch for the in-order core. The transactional memory system's checkpointing mechanism is leveraged to recover from errors. The resulting system runs up to 2.9 times faster than a lockstep system consisting of two in-order cores and consumes up to 35% less energy at the same performance than a lockstep system consisting of two out-of-order cores.