An accelerated electromigration life-test method has been developed to evaluate the large electromigration resistance of Cu interconnects in a ve~. short period of test time. The essence of the acceleration technique employed here is to use stress current more. than 107 A/cm 2 and to utilize the self-heating of the test interconnect for giving temperature stress. Moreover, to avoid uncontrollable thermal runaway and resultant interconnect melting, we adopted an efficient cooling technique that immediately removes the joule heat and keeps the interconnect temperature constant. As a result, it has been demonstrated that large grain copper interconnects created by a low-kinetic-energy particle process and the thermal annealing that follows exhibit approximately three orders of magnitude larger electromigration lifetime at 300 K than Al-alloy interconnects formed by a conventional sputtering process. Additionally, a new expression for electromigration lifetime was proposed based on Black's equation through the comparative studies of electromigration endurance of various materials.Enhancement in integration density and speed performance of ULSI circuits requires miniaturization of transistors and interconnects as well as higher current driving capabilities for transistors. As a result, large currents must be conducted through long interconnects with small cross sections. Therefore the establishment of a metallization scheme which ensures high electromigration reliability as well as low interconnect resistance is important.Aluminum-based alloys, such as A1-Si and A1-Si-Cu, are major materials used to form interconnects in integrated circuits. However, their resistivities are not low enough to operate ULSI circuits at ultrahigh speed. Furthermore, these alloys are liable to show high susceptibility to electromigration and stress-migration failures. Copper(Cu) is drawing considerable attention as an alternative to A1 alloys due to its low bulk resistivity (1.72 ~ 9 cm) and large electromigration resistance. 1 We have reported the establishment of a high performance copper metallization technology by employing a low-kinetic-energy particle process. 2' 3 Cu films deposited on SiO2 with relatively high ion bombardment energies undergo crystal orientation conversion from Cu(lll) to Cu(100) upon thermal annealing, which is accompanied by the growth of giant grains as large as 100 ~m. 3 The room temperature resistivity of such giant-grain Cu films is 1.76 ~ 9 cm which is almost equal to the bulk resistivity of 1.72 ~s -cm. At 12 K, the resistivity is reduced further to 18.3 n~ 9 cm, due to the reduction in the grain-boundary scattering. Such a low resistance feature of Cu films is attractive in the formation of interconnects for high speed LSIs. However, the evaluation of electromigration resistance of Cu interconnects so far has not been conducted extensively due to the difficulty in conducting life tests within a reasonable span of testing time. The conventional technique for accelerated life test of metal interconnects is g...
This paper presents a technique to pattern materials in deep holes and/or on non-planar sub,clinic surfaces. A rather old technique, namely, electron-beam evaporation of metals through a shadow mask, is used. The realization of high-resolutian shadow masks using mieromachining techniques is described. Further, a low ohmic electrical wafer fred-through with a small parasitic capacitance to the substrate and a high placing density is presented.
We have studied a triple-dot single-electron device that includes four series tunnel junctions connecting a source, three islands and a drain, and three capacitive couplings connecting a gate to the three islands. Algebraic solutions for voltage distribution and Coulomb blockade (CB) conditions were derived for the triple-dot device with a homogeneous tunnel capacitance C j and a homogeneous gate capacitance C g . With the help of the established formulas, stability diagrams for the device were drawn and device operating modes were investigated in detail. Stability regions for n ðn 1 ; n 2 ; n 3 Þ ¼ ð0; 0; 0Þ and n ¼ ð0; 1; 0Þ have the shapes of a rhombus and a kite, respectively, and are located along the V g axis. They overlap and a cycle of alternating gate voltage can transfer a single electron from the source to the drain through the islands, that is, the device works as a single-electron turnstile even though it has uniform capacitances. The turnstile operation is possible for any C g =C j ratio. If C g =C j is less than ffiffiffi 2 p À 1, stability regions for n ¼ ð1; 0; 0Þ and n ¼ ð0; 0; 1Þ exist but they do not affect the turnstile operation.
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