As device dimensions continue to shrink, and the number of interconnect layers continues to increase, the resulting surface topography causes serious problems in device patterning (i.e., lithography and etch). CMP has become a standard technology in semiconductor manufacturing to planarize the surface topography. It has been widely reported that the doped silicon oxides, such as phosphosilicate glass (PSG) and borophosphosilicate glass (BPSG), are used for premetal dielectrics (PMD). Phosphorous acts as a gettering center for alkali metals and thus minimizes the impurity penetration into transistors. Since both P 2 O 3 and P 2 O 5 are softer glasses than SiO 2 , the incorporation of P 2 O 3 and P 2 O 5 into the SiO 2 network softens the film. As a result, PSG has a much higher removal rate than undoped silicon oxide. Although several papers in the literature discuss the polishing of PSG, 1-3 several manufacturing issues have not been completely addressed yet. For example, Han et al. illustrates that doped silicate oxides present higher potassium and calcium contamination after scrubbing and deionized (DI) water rinse compared to undoped oxides. 3 This occurs because the phosphorous acts as a gettering site for metal impurities on the surface. In the literature, HF immersion has been reported to reduce the metallic contamination for undoped oxides. 4-7 HF immersion can effectively remove some metal species which are chemically adsorbed onto the oxide surface. Addition of HF in the post-CMP cleaning sequence may be able to remove the metallic contamination on the PSG surface. However, the soft films (such as PSG) tend to have high post-CMP defect counts after an extended HF immersion: HF etches microscratches isotropically and thus enlarges their size, so that more defects are detected after an extended HF immersion. We need to optimize the cleaning process in order to minimize the post-CMP defectivity and metallic contamination.Another issue we discuss here is global planarity. In practice, most CMP processes are developed on unpatterned wafers to optimize the within wafer nonuniformity (WIWNU). Patterned wafers are then polished using such an optimized CMP process. It is a common practice to use step height measurements on the patterned wafers to justify the planarity of the CMP process. Recently, Fang et al. discovered that step height is not necessarily a good criterion to justify the CMP process. 8 Different CMP processes can have similar reduction rates on step height, but the within die nonuniformity (WIDNU) can be completely different. Moreover, one can reach different conclusions about different CMP processes by measuring different locations within a die. 8,9 Typically step height measurements are taken with scans at least 1000-2000 m wide, but this is still not enough to capture the global CMP pattern density effect. Instead of using step height measurements to justify the CMP process, we discuss the effect of polishing parameters on the WIDNU, which represents a more global polishing effect. Since PMD is...
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