Due to the increasing heterogeneity in network user requirements, dynamically varying day to day network traffic patterns and delay in network service deployment, there is a huge demand for scalability and flexibility in modern networking infrastructure, which in return has paved way for the introduction of Software Defined Networking (SDN) in core networks. In this paper, we present an FPGA-based switch which is fully compliant with OpenFlow; the pioneering protocol for southbound interface of SDN. The switch architecture is completely implemented on hardware. The design consists of an OpenFlow Southbound agent which can process OpenFlow packets at a rate of 10Gbps. The proposed architecture speed scales up to 400Gbps while it consumes only 60% resources on a Xilinx Virtex-7 featuring XC7VX485T FPGA.

Convolutional Neural Networks (CNNs) are widely used in deep learning applications, e.g. visual systems, robotics etc. However, existing software solutions are not efficient. Therefore, many hardware accelerators have been proposed optimizing performance, power and resource utilization of the implementation. Amongst existing solutions, Field Programmable Gate Array (FPGA) based architecture provides better cost-energyperformance trade-offs as well as scalability and minimizing development time. In this paper, we present a model-independent reconfigurable co-processing architecture to accelerate CNNs. Our architecture consists of parallel Multiply and Accumulate (MAC) units with caching techniques and interconnection networks to exploit maximum data parallelism. In contrast to existing solutions, we introduce limited precision 32 bit Q-format fixed point quantization for arithmetic representations and operations. As a result, our architecture achieved significant reduction in resource utilization with competitive accuracy. Furthermore, we developed an assembly-type microinstructions to access the co-processing fabric to manage layer-wise parallelism, thereby making re-use of limited resources. Finally, we have tested our architecture up to 9x9 kernel size on Xilinx Virtex 7 FPGA, achieving a throughput of up to 226.2 GOp/S for 3x3 kernel size.

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The use cases involving single or multiple Unmanned Aerial Vehicles (UAVs) controlled by a pilot or operating autonomously are becoming more and more common these days. To support UAVs' safe and efficient operations, the enablement of cooperative awareness (CA) is crucial. In this paper, we approach this challenge by proposing a modification of the Cooperative Awareness Message (CAM) protocol developed by the European Telecommunications Standards Institute (ETSI) for enabling CA for Intelligent Transportation Systems (ITSs) to support UAVs. First, we identify the information required to provide UAV CA. Then, we introduce a messaging architecture with data fields specifically designed to support 3D mobility. We follow the rules of the existing CAM specification so that the proposed messaging structure can be added with minimum modifications to the existing CAM structure. Finally, we assess the proposed modified CAM operating performance on top of the physical (PHY) and medium access control (MAC) layers specified by the IEEE 802.11p radio access technology, which is widely used for vehicular communications. Our results show that air-to-air communications can be effectively used and provide coverage up to 150 m distance with 64-QAM and 1200 m with BPSK modulations. Furthermore, analysis of the MAC layer suggests that the technology can offer a packet reception probability above 0.9 for 10000 UAVs in the same area transmitting at 1 Hz frequency and 800 devices at 10 Hz transmission frequency.