The automatic identification of a corresponding photo from a face sketch can assist in criminal investigations. The face sketch is rendered based on the descriptions elicited by the eyewitness. This may cause the face sketch to have some degrees of shape exaggeration that make some parts of the face geometrically misaligned. In this paper, we attempt to address the effect of these influences by a cascaded static and dynamic local feature extraction method so that the constructed feature vectors are built based on the correct patches. In the proposed method, the feature vectors from the local static extraction on a sketch and photo are matched using the nearest neighbors. Then, some n most similar photos are shortlisted based on the nearest neighbors. These photos are eventually re-matched using feature vectors from the local dynamic extraction method. The feature vectors are matched using the L 1 -distance measure. The experimental results for The Chinese University of Hong Kong (CUHK) Face Sketch Database (CUFS) and CUHK Face Sketch FERET Database (CUFSF) datasets indicate that the proposed method outperforms the state-of-the-art methods.INDEX TERMS Cascaded feature extraction, identity of interest, local feature extraction, sketch to photo, static and dynamic, deep learning.
An automatic photo retrieval system based on a face sketch has very useful application as to narrow down potential suspects in criminal investigations. This is true when there is no other evident except the face sketch that is rendered based on the recollection of a victim or eyewitness. Among the noticeable difficulties in matching the sketch and photo due to its modality difference are the generated sketch has some tendency of shape exaggeration, the sketch has very less accurate details and the real-world photo may expose to lighting variation unlike the sketch. In this paper, we attempt to address these complications by matching the sketch and photos using dynamic local feature of Difference of Gaussian Oriented Gradient Histogram (DoGOGH) on some selected patches. To avoid discriminative power degradation due to a large number of gallery images, two stage matching blocks are introduced in a cascaded fashion. The front block matches the feature such that it short lists k most similar photos for the second block. In this front block, Histogram of Oriented Gradient (HOG) and Gabor Wavelet (GW) features are fused by maximizing the correlation between the two using Canonical Correlation Analysis (CCA). Based on the short listed photos, the following block re-matched the sketch and photos using dynamically extracted local feature on its Patch of Interest (PoI). Eventually, the matching scores from the blocks are fused before getting rank-1 accuracy. The experimental results on two baseline datasets indicate that the proposed method outperforms the stateof-the-art methods. The extended evaluation on semi-forensic and forensic sketch datasets demonstrate its usage feasibility.
Multilevel inverters are a type of power electronic circuit that converts direct current (DC) to alternating current (AC) for use in high-voltage and high-power applications. Many recent studies on multilevel inverters have used field-programmable gate arrays (FPGAs) as a switching controller device to overcome the limitations of microcontrollers or DSPs, such as limited sampling rate, low execution speed, and a limited number of IO pins. However, the design techniques of most existing FPGA-based switching controllers require large amounts of memory (RAM) for storage of sampled data points as well as complex controller architectures to generate the output gating pulses. Therefore, in this paper, we propose two types of FPGA-based digital switching controllers, namely selective harmonic elimination (SHE) and sinusoidal pulse width modulation (SPWM), for a 21-level multilevel inverter. Both switching controllers were designed with minimal hardware complexity and logic utilisation. The designed SHE switching controller mainly consists of a four-bit finite state machine (FSM) and a 13-bit counter, while the SPWM switching controller employs a simple iterative CORDIC algorithm with a small amount of data storage requirement, a six-bit up-down counter, and a few adders. Initially, both digital switching controllers (SHE and SPWM) were designed using the hardware description language (HDL) in Verilog codes and functionally verified using the developed testbenches. The designed digital switching controllers were then synthesised and downloaded to the Intel FPGA (DE2-115) board for real-time verification purposes. For system-level verification, both switching controllers were tested on five cascaded H-Bridge circuits for a 21-level multilevel inverter model using the HDL co-simulation method in MATLAB Simulink. From the synthesised logic gates, it was found that the designed SHE and SPWM switching controllers require only 186 and 369 logic elements (LEs), respectively, which is less than 1% of the total LEs in an FPGA (Cyclone IV E) chip. The execution speed of the SHE switching controller implemented in the FPGA (Cyclone IV E) chip was found to be a maximum of 99.97% faster when compared with the microcontroller (PIC16F877A). The THD percentage of the 21-level SHE digital switching controller (3.91%) was found to be 37% less than that of the SPWM digital switching controller (6.17%). In conclusion, the proposed simplified design architectures of SHE and SPWM digital switching controllers have been proven to not only require minimal logic resources, achieve high processing speeds, and function correctly when tested on a real-time FPGA board, but also generate the desired 21-level stepped sine-wave output voltage (± 360 VPP) at a frequency of 50 Hz with low THD percentages when tested on a 21-level cascaded H-Bridge multilevel inverter model.
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