This paper presents a Multi-Processor System-on-Chip platform which is capable of load balancing at run-time. The system is purely distributed in the sense that each processor is capable of making decisions on its own, without having relying by any central unit. All the management is ensured by a very tiny preemptive RTOS (run-time operating system) running on every processor which is mainly responsible for running and distributing tasks among the processing elements (PEs). The goal of such strategy is to improve the performance of the system while ensuring scalability of the design. In order to validate the concepts, we have conducted some experiments with a widely used multimedia application: the MJPEG (Motion JPEG) decoder. Obtained results show that the overhead caused by the task migration mechanism is amortized by the gain in term of performance.
In this paper, a new concept for a very flexible and modular prototype platform for rapid prototyping of wireless sensor networks is presented. We propose to use a FPGA with high gate count as core of the platform. The FPGA is utilized to attain 3 major goals for the prototype platform: to emulate arbitrary mote architectures even including smart motes with high system complexity, to realize flexible interfaces to sensors and radio transceivers, and to embed versatile debugging and system monitoring functionality in the mote prototypes. The presented prototype platform is suitable to realize complete sensor networks based on different mote architectures, different wireless communication schemes, and arbitrary application domains. The design concepts and implementation aspects of the platform are presented and discussed in detail.
Multiprocessor Systems-on-Chips (MPSoCs) offer superior performance while maintaining flexibility and reusability thanks to software oriented personalization. While most MPSoCs are today heterogeneous for better meeting the targeted application requirements, homogeneous MPSoCs may become in a near future a viable alternative bringing other benefits such as run-time load balancing and task migration. The work presented in this paper relies on a homogeneous NoC-based MPSoC framework we developed for exploring scalable and adaptive on-line continuous mapping techniques. Each processor of this system is compact and runs a tiny preemptive operating system that monitors various metrics and is entitled to take remapping decisions through code migration techniques. This approach that endows the architecture with decisional capabilities permits refining application implementation at run-time according to various criteria. Experiments based on simple policies are presented on various applications that demonstrate the benefits of such an approach.
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