Recently, Multicore systems use Dynamic Voltage/Frequency Scaling (DV/FS) technology to allow the cores to operate with various voltage and/or frequencies than other cores to save power and enhance the performance. In this paper, an effective and reliable hybrid model to reduce the energy and makespan in multicore systems is proposed. The proposed hybrid model enhances and integrates the greedy approach with dynamic programming to achieve optimal Voltage/Frequency (Vmin/F) levels. Then, the allocation process is applied based on the available workloads. The hybrid model consists of three stages. The first stage gets the optimum safe voltage while the second stage sets the level of energy efficiency, and finally, the third is the allocation stage. Experimental results on various benchmarks show that the proposed model can generate optimal solutions to save energy while minimizing the makespan penalty. Comparisons with other competitive algorithms show that the proposed model provides on average 48% improvements in energy-saving and achieves an 18% reduction in computation time while ensuring a high degree of system reliability.
The energy consumption is becoming a constraint on all computer devices, from smartphones to supercomputers. Consequently, the focus has moved from performance to energy and power consumption. Design metrics are not only based solely on performance, as the energy performance of application executions is becoming the main aspect of architecture. Also, Design metrics depend on, the manufacturers of semiconductor chips which, have implemented multicore processors to boost the level of energy efficiency by using verified techniques for voltage and frequency scaling. To utilize the maximum potential of such architectures, we need to make the right decisions because parameters such as core type, frequency, and utilization typically affect power dissipation and performance. This paper proposes a new algorithm to achieve energy-efficient by monitoring core energy and level utilization control such as: Increasing the number of cores to execute the task, scaling voltage, and frequency. Based on the built model, we analyze the energy efficiency variations for different platform configurations providing the same level of performance. We show that trading the number and type of core with frequency and voltage level and core utilization rate can lead to substantial energy efficiency gains.
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