By virtue of its simplicity, clipping appears to be one of the most attractive methods to mitigate Peak to Average Power Ratio (PAPR) in OFDM systems. After positioning clipping in a new classification of PAPR reduction methods, this article focuses on the performance of clipped OFDM at low signal to noise ratio, typical of capacity approaching forward error correcting coded systems. A lower bound on the BER performance of clipped coded OFDM is given and shown to be consistent with the genie aided performance of the iterative clipping noise cancellation receiver. Finally, numerical results on the BER performance of a clipped LDPC coded OFDM system are provided. 1
Iterative processing is widely adopted nowadays in modern wireless receivers for advanced channel codes like turbo and LDPC codes. Extension of this principle with an additional iterative feedback loop to the demapping function has proven to provide substantial error performance gain. However, the adoption of iterative demodulation with turbo decoding is constrained by the additional implied implementation complexity, heavily impacting latency and power consumption.In this paper, we analyze the convergence speed of these combined two iterative processes in order to determine the exact required number of iterations at each level. Extrinsic information transfer (EXIT) charts are used for a thorough analysis at different modulation orders and code rates. An original iteration scheduling is proposed reducing two demapping iterations with reasonable performance loss of less than 0.15 dB. Analyzing and normalizing the computational and memory access complexity, which directly impact latency and power consumption, demonstrates the considerable gains of the proposed scheduling and the promising contributions of the proposed analysis.
Flexible and iterative baseband receivers with advanced channel codes like turbo codes are widely adopted nowadays, ensuring promising error rate performances. Extension of this principle with an additional iterative feedback loop to the demapping function has proven to provide substantial error performance gain at the cost of increased complexity. However, this complexity overhead constitutes commonly an obstacle for its consideration in real implementations. This article illustrates the opposite of what is commonly assumed and proposes a complexity adaptive iterative receiver performing iterative demapping with turbo decoding (TBICM-ID-SSD). Targeting identical error rate, the article shows that for certain system configurations TBICM-ID-SSD presents lower complexity than TBICM-SSD (without iterative demapping). This original result is obtained when considering the equivalent number of iterations through detailed analysis of the corresponding computational and memory access complexity. The analysis is conducted for different parameters in terms of modulation orders and code rates and independently from the architecture for a fair comparison. Considering the proposed adaptive receiver which is able to perform both TBICM-ID-SSD and TBICM-SSD modes, results demonstrate a reduced complexity with TBICM-SSD for high modulation orders. However, for low modulation orders as for QPSK, results show a reduction in arithmetic operations and read access memory up to 45.9% and 47%, respectively for using the TBICM-ID-SSD mode rather than TBICM-SSD performing six turbo decoding iterations over Rayleigh fading channel with erasures.
Flexible baseband receivers gain the interest of many research efforts to enable the design of future multi-modes multistandards terminals. A main challenge in this domain is to provide this flexibility with minimum overhead in terms of area, speed, and energy. In this regard, heterogeneous multiprocessor platforms are emerging as a promising implementation solution. However, the heterogeneity of such platforms makes it complex to find the required number of processors supporting a specific configuration (i.e. requirements level).This paper investigates, in this context, the significant optimization potential both at design-time and at run-time regarding the selection of the most appropriate hardware configuration of a multiprocessor platform for iterative demapping and channel decoding. A formal representation of the architectural solution space which allows designers to find the minimum hardware configuration is proposed. The proposed approach is illustrated through a flexible multi-ASIP hardware platform for iterative demapping and channel decoding.
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