Purpose -Information and communication technologies (ICTs) open new opportunities for micro-enterprises to improve their businesses. However, challenges to using ICTs impede these businesses from growing into drivers for development. This paper seeks to investigate the adoption of ICTs in 11 micro-enterprises in an underserved community of Omaha, Nebraska. Design/methodology/approach -Following an action research study, this research provides insight into the key challenges and opportunities facing micro-enterprises in their use of ICTs to create value for their businesses. Findings -The process of "IT therapy" provides individualized technology-related assistance, with an emphasis on relationship-building, customized training, context sensitivity, and solutions that target strongly-perceived needs of the businesses studied. Originality/value -The paper's contribution is in the methodology for facilitating the adoption of ICTs in micro-enterprises.
Phase Change Memory (PCM) is a promising technology for building future main memory systems. A prominent characteristic of PCM is that it has write latency much higher than read latency. Servicing such slow writes causes significant contention for read requests. For our baseline PCM system, the slow writes increase the effective read latency by almost 2X, causing significant performance degradation.This paper alleviates the problem of slow writes by exploiting the fundamental property of PCM devices that writes are slow only in one direction (SET operation) and are almost as fast as reads in the other direction (RESET operation). Therefore, a write operation to a line in which all memory cells have been SET prior to the write, will incur much lower latency. We propose PreSET, an architectural technique that leverages this property to pro-actively SET all the bits in a given memory line well in advance of the anticipated write to that memory line. Our proposed design initiates a PreSET request for a memory line as soon as that line becomes dirty in the cache, thereby allowing a large window of time for the PreSET operation to complete. Our evaluations show that PreSET is more effective and incurs lower storage overhead than previously proposed write cancellation techniques. We also describe static and dynamic throttling schemes to limit the rate of PreSET operations. Our proposal reduces effective read latency from 982 cycles to 594 cycles and increases system performance by 34%, while improving the energy-delay-product by 25%.
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