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A novel neurostimulator for generating neural code-based, precise, asynchronous electrical stimulation pulses is designed, fabricated, and characterized. Through multiplexing, this system can deliver constant current biphasic pulses, with arbitrary temporal patterns, and pulse parameters to 32 electrodes using one pulse generator. The design also features a stimulus artifact suppression (SAS) technique that can be integrated with commercial amplifiers. Using an array of CMOS switches, electrodes are disconnected from recording amplifiers during stimulation, while the input of the recording system is shorted to ground through another CMOS switch to suppress ringing in the recording system. The timing of the switches used to block and suppress the stimulus artifact are crucial and are determined by the electrochemical properties of the electrode. This system allows stimulation and recording from the same electrodes to monitor local field potentials with short latencies from the region of stimulation for achieving feedback control of neural stimulation. In this way, timing between each pulse is controlled by inputs from an external source and stimulus magnitude is controlled by feed-back from neural response from the stimulated tissue. The system was implemented with low-power and compact packaged microchips to constitute an effective, cost-efficient, and miniaturized neurostimulator. The device has been first evaluated in phantom preparations and then tested in hippocampi of behaving rats. Benchtop results demonstrate the capability of the stimulator to generate arbitrary spatio-temporal pattern of stimulation pulses dictated by random number generators (RNGs) to control magnitude and timing between each individual biphasic pulse. In vivo results show that evoked potentials elicited by the neurostimulator can be recorded ∼2 ms after the termination of stimulus pulses from the same electrodes where stimulation pulses are delivered, whereas commercial amplifiers without such an artifact suppression typically result in tens to hundreds of milliseconds recovery period. This neurostimulator design is desirable in a variety of neural interface applications, particularly hippocampal memory prosthesis aiming to restore cognitive functions by reinstating neural code transmissions in the brain.

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The design, fabrication, and testing of a microelectrode array for chronic in vivo stimulation of the rat retina is presented. Epiretinal positioning of the array introduced design challenges associated with the surgical implantation approach into the rat ocular orbit. These anatomical and surgical challenges were overcome using microfabrication of thin-film Parylene C and platinum to create the array followed by thermal post-processing steps to achieve the required array geometry. An electroplated platinum-iridium coating was employed to increase the electrode charge storage capacity and then verified in benchtop electrochemical characterization. Preliminary in vivo implantations with sham devices containing no metal revealed chronic biocompatibility (up to 6 weeks) and acute trials with functional arrays illustrated device robustness against surgical trauma. This work represents the first epiretinal implant development for the rat animal model via a suitable soft neural interface device enabled through polymer MEMS micromachining.

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Same-electrode stimulation and recording with high spatial resolution, signal quality, and power efficiency is highly desirable in neuroscience and neural engineering. High spatial resolution and signal-to-noise ratio is necessary for obtaining unitary activities and delivering focal stimulations. Power efficiency is critical for battery-operated implantable neural interfaces. This study demonstrates the capability of recording single units as well as evoked potentials in response to a wide range of electrochemically safe stimulation pulses through high-resolution microelectrodes coated with co-deposition of Pt-Ir. It also compares signal-to-noise ratio, single unit activity, and power efficiencies between Pt-Ir coated and uncoated microelectrodes. To enable stimulation and recording with the same microelectrodes, microelectrode arrays were treated with electrodeposited platinum-iridium coating (EPIC) and tested in the CA1 cell body layer of rat hippocampi. The electrodes’ ability to (1) inject a large range of electrochemically reversable stimulation pulses to the tissue, and (2) record evoked potentials and single unit activities were quantitively assessed over an acute time period. Compared to uncoated electrodes, EPIC electrodes recorded signals with higher signal-to-noise ratios (coated: 9.77 ± 1.95 dB; uncoated: 1.95 ± 0.40 dB) and generated lower voltages (coated: 100 mV; uncoated: 650 mV) for a given stimulus (5 μA). The improved performance corresponded to lower energy consumptions and electrochemically safe stimulation above 5 μA (>0.38 mC/cm2), which enabled elicitation of field excitatory post synaptic potentials and population spikes. Spontaneous single unit activities were also modulated by varying stimulation intensities and monitored through the same electrodes. This work represents an example of stimulation and recording single unit activities from the same microelectrode, which provides a powerful tool for monitoring and manipulating neural circuits at the single neuron level.

As computational and functional brain model development are solely dependent upon the data acquired from the neural interface, this device plays a vital role in both prosthetic developments and neurological experiments. A wireless neural interface is preferred over a traditional wired one because it can maximize the comfort of the subject and ensure the freedom of movement while implemented. This paper describes the field programmable gate array (FPGA) prototype design of a low-power multichannel neuron activity extraction unit suitable for a wireless neural interface. To achieve the low-power requirement, we proposed a novel neural signal extraction algorithm which can provide an up to 6000X transmission rate reduction considering the input signal. Consequently, this technique offers at least 2X power reduction compared to the state-of-the-art systems. We implemented this scheme in Xilinx Zynq-7000 FPGA, which can be used as an intermediate transition towards the application specific integrated circuit (ASIC) design for on-chip neural signal processing. The proposed FPGA prototype offers reconfigurable computability, which means the model can be modified and verified according to prerequisites before the final ASIC design. This prototype consists of a signal filtering unit and a signal extraction unit which can be used either as stand-alone units or combined as a complete system. Our proposed scheme also provides a provision to work as a single-channel or a scalable multichannel interface based on user’s demands. We collected practical neural signals from rat brains and validated the efficacy of the implemented system using in-silico signal processing.

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