In this paper a novel method for speed regulation and tracking of Switched Reluctance Motor is proposed. The proposed method uses the concept of only energizing all those phases of the motor which can contribute to desired polarity of torque at one time for power saving. The suggested scheme is based on Sliding Mode Technique. A mathematical model of SR motor is derived for controller design purpose. The power efficiency is derived by not energizing all the phases at a given time; this is because not all the phases of SR motor can produce torque with the same polarity because of the particular motor construction. Thus our controller chooses the appropriate phases, at any control instant, to get the desired torque output with minimum phase currents. The speed regulation scheme is compared with the conventional sliding mode control taken from the public literature. Simulation results confirm the effectiveness of the proposed regulation controller. The proposed scheme reduces the power loss of SR motor. A tracking control based on the new scheme is also presented.
Parallel hardware architectures are used to design turbo-like iterative decoders to meet the requirement of high data rate applications. However, parallel architectures suffer from memory conflict problem due to interleaving law used in turbo-like codes. To solve conflict problem, different memory mapping approaches have been developed. These methods automatically generate a set of control words stored in ROM to drive the architecture. These approaches are used off-chip by the designer (i.e. prior the decoder implementation) to generate different set of control words i.e. one set for each block length used in the target telecommunication standard. This requires multiple ROMs to store mapping information for multiple block lengths and results in huge hardware cost. In this article, we propose to embed memory mapping algorithms on-chip. Hence, each time word-length changes, memory mapping algorithm is executed. Command words are thus generated at runtime and stored in a RAM. This is a first attempt to embed mapping algorithms on chip and experimental results show that a significant amount of memory can be saved by using on-chip execution of mapping algorithms. Results also highlight that improvement in design and implementation of mapping algorithms are still needed to embed mapping algorithms on-chip to implement flexible decoder architectures.
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