A 0.2-pm bipolar-CMOS process technology on a bonded SO1 wafer was developed for ultra-high-speed applications. This process was used to fabricate a new-cache memory chip consisting of 9-Mb 0.6-11s SRAMs and a 200-K 25-ps ECL gate array. To achieve high performance, the 0.2-pm bipolar-CMOS process features a 6-pm2-cell-size BJT with a 50-nm base width, a 6T-CMOS memory cell and copper interconnects that reduce wiring delay by 30%. A combination of low-energy ion-implantation and two-step annealing was applied to form a low-leakage, shallow base junction. A bonded SO1 wafer with deep and shallow trench isolations was used to maximize the BJT performance.
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