A SiGe single-chip 3.3V receiver IC for 10Gb/s optical communication systems integrates a transimpedance preamplifier, a limiting amplifier with a reference voltage generator, and a clock and data recovery (CDR) circuit with a phase-locked loop (PLL). For this IC, phase-comparison automatically adjusts the clock phase to the optimum point for data regeneration in the CDR circuit. The receiver IC uses a SiGe bipolar transistor with 6OGHz cutoff frequency. It operates a t 10Gb/s with 660mW power consumption at 3.3V.There is increasing demand for 10Gb/s ICs in optical links for applications such as computer interconnection. Mass-production yields of Si bipolar circuits are better than those of GaAs ICs. Several Si bipolar ICs such as the lOGHz bandwidth preamplifier-IC and the PLL-ICs for use in 10Gb/s optical communication systems are reported [l-31. The receiver ICs are key components in wavelength division multiplexing (WDM) networks and interconnections [41. Practical receiver IC must be low-cost and small and have low power consumption. These requirements can be met by integrating both amplifier and CDR circuit on a single chip. I t is difficult to operate a phase comparator in a CDR circuit a t 10Gb/s with a 3.3V power supply. A reference voltage is needed a t the limiting amplifier to transform the single-ended preamplifier signal to differential voltage signals a t thelimiting amplifier input.The features of the single chip receiver IC are: (1) the CDR circuit automatically adjusts clock phase t o the optimum point for data regeneration at a data rate of 10Gbls and with a 3.3V power supply using a phase-comparison; (2) a reference voltage generator that provides a reference voltage for DC coupling between a preamplifier and a limiting amplifier; (3) designed for a 3.3V power supply by using a SiGe bipolar transistor with 6OGHz cutoff frequency a t 1V collector-emitter bias. The single-chip receiver IC operates a t lOGb/s a t 3.3V. Figure 22.3.1 shows a block diagram of the overall single chip receiver IC that consists of a preamplifier, a limiting amplifier and a CDR circuit with a PLL. Current signals from the photodiode are transformed to voltage signals in the preamplifier. A limiting amplifier is selected instead of an automatic-gain-control (AGC) amplifier which requires a higher voltage supply. The reference voltage for DC-coupling between the preamplifier and the limiting amplifier is generated by the reference voltage generator. The limiting amplifier outputs differential voltage signals to the CDR circuit. The CDR circuit extracts a clock from nonreturn-to-zero (NRZ) input data and outputs regenerated data.The CDR circuit is key in the single-chip receiver. There are several CDR operating techniques, however adjusting the clock phase to the optimum point for data regeneration is difficult with this circuit 151. A solution to this problem is post-processing the inputs and outputs of cascaded flip-flops [61. In that scheme, however, the circuit fails to operate properly as the clock speed increases. F...
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