Recent discovery of ferroelectricity in HfO2 thin films paved the way for demonstration of ultra-scaled 28 nm Ferroelectric FETs (FeFET) as non-volatile memory (NVM) cells [1]. However, such small devices are inevitably sensible to the granularity of the polycrystalline gate oxide film. Here we report for the first time the evidence of single ferroelectric (FE) domain switching in such scaled devices. These properties are sensed in terms of abrupt threshold voltage (VT) shifts leading to stable intermediate VT levels. We emphasize that this feature enables multi-level cell (MLC) FeFETs and gives a new perspective on steep subthreshold devices based on ferroelectric HfO2
circuits. [2,3] The fine-grain reconfiguration approaches aim at the reduction of routingrelated delays and chip area reduction. A very interesting fine-grain approach that emerged during the last decade is based on polarity programmable or reconfigurable field-effect transistors (RFETs). RFETs have been highlighted due to their novel functionality providing both n-type and p-type field-effect transistor (FET) function in a single device selected simply by an electric signal. [4][5][6][7][8][9] Up to date, reconfigurable transistors have been limited to dynamic programming on the function, i.e., a constant program signal needs to be applied to maintain the required function.However, a nonvolatile component that can be embedded into these reconfigurable logic devices would not only eliminate the requirement of having the configuration voltage applied continuously but would also bring additional advantages in terms of multivalent memory operation and close proximity between memory and logic. A number of demonstrations of nanowire-based nonvolatile memory cells have been reported in literature. [10][11][12] In these realizations, the channel polarity of the memory cell is determined by the doping type of silicon. First demonstrators of nonvolatile reconfigurable device operation were shown with the use of a common back gate electrode; [13] in the work by Schwalke et al., the charge trapping is performed using the buried oxide while a high voltage is applied to the global back gate. With this approach, it is difficult to individually address the desired device and to perform other operations in the chip, while writing/erasing some of the devices. Recently, a poly-Si reconfigurable device with a bottom gate array was also demonstrated and showed nonvolatile functionality. [14] In this work, the first demonstration of individually addressable nonvolatile RFETs based on bottom-up grown Si nanowire is presented. Figure 1 shows a schematic design and a crosssectional transmission electron micrograph (TEM) image of the fabricated and measured device. We make use of charge trapping in the gate stack of a dedicated gate electrode. As a vehicle to verify our proof of principle, we integrated the technologically lean charge trapping metal-nitride-oxide-silicon (MNOS) gate stack. The validity of the MNOS stack for nonvolatile charge storage, in general, is well accepted in the memory community. [15,16] For simplicity, in demonstrating the concept, we use a rather thick Si 3 N 4 layer of 15 nm and omit the use of a top blocking oxide. In this configuration, the top part of the thick trapping layer has the same electrostatic function as the blocking oxide in the silicon-oxide-nitride-oxide-silicon Reconfigurable transistors merge unipolar p-and n-type characteristics of field-effect transistors into a single programmable device. Combinational circuits have shown benefits in area and power consumption by fine-grain reconfiguration of complete logic blocks at runtime. To complement this volatile programming technology, a proof of ...
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