Maintaining metro ridership in the future will require an increasing focus on customer perceptions of the service quality. This work outlines a process whereby passenger expectations may be encapsulated into a mathematical evaluation function that can then be used in an on-line optimization procedure. The function proposed penalizes excess waiting time, travelling time and congestion following a disturbance such as a platform delay. With the function defined, the problem resolves into finding a set of optimum arrival and departure times (the decision variables) that minimizes this penalty function. Ultimately, the concept is intended to form part of an on-line, real-time traffic controller residing on the despatching computer in a control centre. An embedded simulation is used to perform the optimization calculations, and several techniques are described that reduce the computing time needed to a level feasible for on-line use. Comparisons are made with some previous control algorithms. Using data based on the Hong Kong Island Line, it is shown that the new controller performs well, albeit when using the newly proposed evaluation function as the test criterion.
This paper describes the design of a masterslice LSI with two‐input equivalent 6000 gates (three‐input 4000 gates). It uses 2 μm CMOS dual Al interconnect process technology and has application to medium and small computers, terminals and peripheral equipment. It is shown that a three‐input bent‐type gate basic cell effectively realizes high integration because various logic gates can be constructed with small areas. to realize high speed, the chip is designed in several blocks. the intra‐block net uses short interconnects, whereas the inter‐block net is driven by buffers with high load drive capability. Special clock supply circuits for small clock signal skew and a register‐file to accommodate a small capacity RAM into LSI are designed. the number of wiring channels is determined based on the theoretical wiring length, and it has been confirmed that channel utilization agrees with the theoretical value. Since it is important that a masterslice LSI be designed to its specifications within a short time, a method is developed to calculate accurately the circuit delay time during the design. Evaluation of the test LSIs shows that the average gate delay time of 1.81 ns is obtained; this agrees to within 5.4% of the calculated delay time.
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