This paper investigates the influence of the N-type buried layer (NBL) layout and LOCOS space on the ESD performance and trigger voltage of the lateral DMOS (LDMOS) device. Without adequate LOCOS spacing, LDMOS is vulnerable to ESD damage. If the LOCOS space is sufficiently wide, adding NBL structure can further improve LDMOS ESD performance significantly. This is because NBL can switch the current passage from the surface channel region to the bulk NBL during an ESD zapping, thus, avoiding localized highly damaging ESD current flow in the channel region.
Degradation of lateral diffused MOS transistors in various hot-carrier stress modes is investigated. A novel threeregion charge-pumping technique is proposed to characterize interface trap (N it ) and bulk oxide charge Q ox creation in the channel and in the drift regions separately. The growth rates of N it and Q ox are extracted from the proposed method. A two-dimensional numerical device simulation is performed to gain insight into device degradation characteristics in different stress conditions. This paper shows that a maximum I g stress causes the largest drain current and subthreshold slope degradation because of both N it generation in the channel and Q ox creation in the bird's beak region. The impact of oxide trap property and location on device electrical characteristics is analyzed from measurement and simulation.Index Terms-Hot-carrier degradation, lateral diffused MOS (LDMOS), three-region charge pumping (CP).
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