Interface defects generated by negative-bias temperature stress (NBTS) in an ultrathin plasma- nitrided SiON/Si(100) system were characterized by using D2 annealing, conductance-frequency measurements, and electron-spin resonance measurements. D2 annealing was shown to lower negative-bias temperature instability (NBTI) than H2 annealing. Interfacial Si dangling bonds (Pb1 and Pb0 centers), whose density is comparable to an increase in interface trap density, were detected in a NBTS-stressed sample. The NBTI of the plasma-nitrided SiON/Si system was thus shown to occur through Pb depassivation. Furthermore, the nitridation was shown to increase the Pb1/Pb0 density ratio and modify the Pb1 structure. Such a predominance and structural modification of Pb1 centers are presumed to increase NBTI by enhancing the Pb–H dissociation. Although we suggest that NBTS may also induce non-Pb defects, nitrogen dangling bonds do not seem to be included in them.
We have developed 65nmnode CMOS technology for generalpurpose systemdnaship (SoC), in which both standby and active power reductions are strongly required. With highly reliable triple gate oxide ( 1 . 3~ 1.6nm and 3.2nm) using low damage process, an average standby current can be reduced to one-fifth compared with conventional case. Gate predoping and RTA conditions were optimized to maintain oniurrent even with the supply voltage of 0.9V. Highspeed (HS) transistors show on-currcnt of 6 8 0 p N~m for nFET and 240pNpm for pFET with 5 of 13nA/pm and I , , = of 30nAipm. Low-gateieakage (LGL) transistors show on-current of 490pNpm for nFET and 1 7 5~N p m for pFET with 5 of 0 . 8 N p m and Io= of 3nA/pm. Gate oxide of all the above transistors exhibit tight TDDB distributions.
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