SUMMARYFast, highly accurate A-D converters have recently been required in measurement for wireless communications. The time-interleaved A-D converter, in which multiple highly accurate A-D converters with relatively low speed are combined and are operated by clocks with phase shifts, is known to be effective in the realization of such devices. On the other hand, the following problems have been pointed out. Due to the mismatched characteristics of the A-D converters for the respective channels, the performance of the time-interleaved A-D converter as a whole is degraded. The sampled value is fluctuated by the error in the time domain. In the frequency domain, the spurious level increases, and the spurious-free dynamic range (SFDR) is degraded. In order to reduce the effect of mismatch of characteristics, this paper proposes a method of reducing the nonlinear error contained in the sample values by applying an Estimation Equalizing Technique to the sampled values of the time-interleaved A-D converter, making use of the frequency characteristics of each channel, which are measured by undersampling. The effectiveness of the proposed method is demonstrated by simulation and experiment.
Recent developments in memory devices have led to the proposal of a direct method of constructing combinatorial logic filter which uses bit serial operation (i.e., memory and reversible adder are used for bitwise summing of the result of weighted addition). By combinatorial construction it is possible to increase operating speed, simplify the hardware and decrease the power consumption, leading to an efficient digital filter. This paper applies bit serial operation to the canonical construction, leading to a combinatorial filter with memory capacity of 1/2N‐1. Then, bit parallel‐serial operation, which sums up the result of multibit weighted addition, is applied to the canonical construction of the second‐order section, leading to a digital filter with t/I times higher speed than in the past. It is noted that the roundoff noise in the combinatorial filter is independent of the input data, and a noise evaluation model is proposed in which the error can be independently discussed. Using the proposed model, the mean‐square error of the filter output can easily be determined. This paper deals with the drawbacks in the past theory of noise evaluation for the direct construction and performs a noise analysis for the canonical construction. The result is useful in application to LSI design for a high‐speed digital filter.
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