H.264/AVC is a new recommendation for moving picture coding, in which a lot of new techniques are used for improving encoding efficiency and reducing the bit-rate. However, it involves an exhaustive motion search across multiple block sizes and multiple reference frames leading to a linear increase in processing time. Although, the encoding quality is improved, the complexity of the encoder and computational cost are increased at the same time. We reduce the computational cost by reducing the search space without significant loss in quality. Results show that there is at least 90% reduction in computation with a maximum loss of 1.4dB.
We present a novel motion estimation engine (MEE) architecture that efficiently reuses search area data while fully utilizing the hardware resources. A 2-D processing element (PE) core is central to the architecture. Search area data flows both horizontally as well as vertically while the current block data is stationary. A clever PE design ensures simple but highly regular dataflow through the core avoiding long interconnect delays. For a search range of [-16,+15] and block size of 16, our architecture can perform motion estimation for 60 fps of 4CIF video at 100 Mhz.
INTRODUCTIONMotion-compensated transform coding has been adopted by all of the existing international standards related to video coding, such as the ISO MPEG series and the ITU-T H.26x series as well as the latest H.264/AVC. For a video coding system, motion estimation (ME) can remove temporal redundancy within frames so that a high compression ratio can be achieved. Block matching algorithms are the most popular method for ME and are widely adopted in the standards because of their simplicity and good performance. Numerous pixel by pixel difference operations are central to the block matching algorithms and result in high computational complexity and huge memory bandwidth. Among all block matching algorithms, full-search block matching algorithm (FSBMA) is the most popular. Although it provides the best quality amongst various ME algorithms and is straightforward, it demands the most computation. Most recently, the H.264/AVC standard has recommended a lot of features to improve the ME. The encoder can use seven different block sizes for ME [1]. As a result the processing time increases linearly with the number of block types used. This is because ME needs to be performed for each block type. The process of examining all seven block types provides the best coding result but makes the process computationally intensive. Besides this, the H.264/AVC standard supports half-pel and quarter-pel accurate motion search. It also supports multiple numbers of reference frames. These features not only increase the coding efficiency and motion vector (MV) accuracy but furthermore elevate the computational requirement. In a typical video coding system, the ME module is the most computationally intensive operation constituting of about 70%-90% of the entire computational load [2]. Therefore having a fast hardware accelerator for ME is highly desirable.FSBMA is the most suitable candidate for implementation in hardware. Many parallel and pipelined VLSI architecture designs for FSBMA have been developed due to its regular data flow. One of the first discussions about FSBMA architectures was presented in [3]. A survey of VLSI architectures is also presented in [4] and more recently, the authors of [5] present a classification for FSBMA architectures based on data reuse level (Level A, B, C, and D). All these architectures either use 1-D systolic arrays, 2-D systolic arrays [7,8], or tree-structured architectures to implement FSBMA. The processing capability...
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