The artificial intelligence-based MEMS switch designs have been led technology in present micro-electronic applications. The 4G and 5G communication hardware networks have working been through RF-MEMS switches. The earlier MEMS deigns are outdated in terms of functionality and compatibility, so that a realistic RF-MEMS based advanced configurations are compulsory for future electronic applications. In this research work 2 different shunt-capacitive type configurations have been implemented and those are verified on COMSOL Multi-physics toolbox as well as functionality been verified on HFSS software tool. The electromechanical properties of proposed shunt type RF-MEMS switch attained more perfection in functionality compared to past configurations. The implemented switching model has uniform meandering and derives pull-in-voltage of 18.5v along with 1.2xs switching time. The 2nd type shunt RF-MEMS model has been generated pull-in-voltage of 25.5v and isolation loss of 37.20. The performance metrics like Length 25.34 μm, Width 28.92 μm and Thickness 34.42 μm had been improved compared to previous models. The deigned shunt-capacitive type RF-MEMS models are most prominent in operation and offering advanced microelectronics applications.
The logarithmic number system (LNS) can be used to simplify the computation of arithmetic functions, such as multiplication. This article proposes three leading-one detectors (LODs) to speed up the binary logarithm calculation in the LNS. The first LOD (LOD I) uses a single fixed value to approximate the d least significant bits (LSBs) in the outputs of the LOD. The second design (LOD II) partitions the d LSBs into smaller fields and uses a multiplexer to select the closest approximation to the exact value. These two LODs help with error cancellation as they introduce signed errors for inputs N < 2 d . Additionally, a scaling scheme is proposed that scales up the input N < 2 d to avoid large approximation errors. Finally, an improved exact LOD (LOD III) is proposed that only passes half of the input N to the LOD; the more significant half is passed if there is at least one '1' in that half; otherwise, the less significant half is passed. Our simulation results show that the 32-bit LOD III can be up to 2.8� more energy-efficient than existing designs in the literature. The Mitchell logarithmic multiplier and a neural network are considered to further illustrate the practicality of the proposed designs.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.
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