The Hyper Suprime-Cam (HSC) is an 870 megapixel prime focus optical imaging camera for the 8.2 m Subaru telescope. The wide-field corrector delivers sharp images of 0${^{\prime\prime}_{.}}$2 (FWHM) in the HSC-i band over the entire 1${^{\circ}_{.}}$5 diameter field of view. The collimation of the camera with respect to the optical axis of the primary mirror is done with hexapod actuators, the mechanical accuracy of which is a few microns. Analysis of the remaining wavefront error in off-focus stellar images reveals that the collimation of the optical components meets design specifications. While there is a flexure of mechanical components, it also is within the design specification. As a result, the camera achieves its seeing-limited imaging on Maunakea during most of the time; the median seeing over several years of observing is 0${^{\prime\prime}_{.}}$67 (FWHM) in the i band. The sensors use p-channel, fully depleted CCDs of 200 μm thickness (2048 × 4176 15 μm square pixels) and we employ 116 of them to pave the 50 cm diameter focal plane. The minimum interval between exposures is 34 s, including the time to read out arrays, to transfer data to the control computer, and to save them to the hard drive. HSC on Subaru uniquely features a combination of a large aperture, a wide field of view, sharp images and a high sensitivity especially at longer wavelengths, which makes the HSC one of the most powerful observing facilities in the world.
Charge-coupled device (CCD) technology is the traditional route to realization of high-end consumer-level color imaging products. Device count and complexity militate against the price/performance breakthrough necessary to bring cameras for videoconferencing, digital stills and movie photography to the mass-market. Recently, a technological alternative to CCD in the form of cameras using sensors built from standard CMOS processes has appeared, and we report here a further milestone. A single-chip NTSC video camera can be partitioned into analog (custom) and digital (cell-based) sections ( Figure 1) [1,21.Thesensingheart ofthedeviceisanarrayof306~244photosensitive elements, each comprising a 3 transistor active pixel based on a standard CMOS n +/ p-well photodiode ( Figure 2). Photocharge integrated in the pixel during exposure is read row-sequentially into a column structure that removes the systematic offset of each pixel by a read sequence with correlated double sampling. The row of corrected values is then read pixel-sequentially, synchronous to the color processing engine through a programmable gain amplifier to a samplehold stage that drives an onboard 8b half-flash sub-ranging ADC. The resulting digital video stream is sent to the color processing engine, that returns an NTSC encoded data stream for conversion to analog by a currentsteering DAC driving 1V composite video into a 37.5Q load. Alternating progressive-scan field exposures comply with 525line 29.97Hz NTSC frame timing [31.The device contains all voltage references and analog signal buffers needed t o render the final device autonomous. I t requires only a few decoupling capacitors and terminating resistors in addition to a single crystal (Figure 3). To this end, two control loops utilize statistics gathered in the digital section of the device to maintain optimal analog operation. Auto black calibration (ABC) monitors nominal black lines in the image, using a small DAC to calibrate out offsets and center the black level at the bottom of the ADC range. Automatic exposure control (AEC) determines both charge integration time and gain. The exposure of a non-shuttered CMOS sensor can be considered as a rolling window of a certain number of lines, represented by a pulse traversing the vertical shift register. It is also possible to use line section to give a finer exposure step, resulting in a potential exposure range from one field (16.7ms) to one pixel (140ns), a range of almost 120,OOO:l. 18dB of digitally-selectable analog gain is also available.Aside from the sensor control logic described above, the digital section comprises two essentially independent signal-processing modules that process data at 14.32MHz in dataflow architecture to achieve a throughput of over 300M integer operationsk (8b add equivalent). Arithmetic is performed in serial-parallel carry-ripple pipelines, with embedded lookup of non-linear functions [4]. Five line memories are included for vertical filtering.The color reconstruction processor recovers 24b RGB data from Bayer-p...
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