In deep sub-micron era, many semiconductor fabrication process variations highly relate to uniformity of IC layout design. Chemical-polishing process and Flash Lamp Anneal (FLA) are two of the crucial processes aiming to increase uniformity of IC. Dummy filling is an efficient and effective Design for Manufacturability method for increasing layout uniformity by filling non-functional dummy shapes onto unoccupied area and thus reducing pattern-induced process variation. However, none are design for the thermal effects of FLA process. FLA process annealed the wafer in high temperature (1250 • C) in a few milliseconds. Wafer surface emissivity determines the amount of heat absorption during FLA process. The temperature variation of FLA process induced by surface emissivity variation of IC layout results in shifts of transistors' electrical parameters. This paper proposed to use genetic algorithm to minimize the emissivity variation of IC layout by filling a series of prescribed dummy patterns with various emissivity. The experimental results from twenty test cases show that 35% emissivity variation reductions can be achieved and moreover the observed temperature deviation during FLA is under 2.8%.
During the research and development (R&D) stage of semiconductor fabrication, the R&D engineers make a lot of effort to identify golden dice that meet simulated performance of circuit design. With feedback from wafer acceptance test (WAT) data of the golden dice, the efficiency of process window analysis can be further improved. However, it is difficult for current practices to select golden dice due to limited time and cost concerns. In this research, an analytical model is proposed to analyze WAT data during the R&D stage of semiconductor fabrication to assist R&D engineers in resolving these critical issues. WAT data are collected and utilized to classify dice on a wafer and similar golden dice are then identified based on pre-defined golden dice. Similar golden dice can provide much more important feedback from WAT data, and the efficiency of process window analysis can then be improved. Real WAT data at the R&D stage during semiconductor fabrication were collected from a famous semiconductor manufacturing company and were experimented through the presented methodology. Experimental results show that the presented model can successfully extract representative similar golden dice within clusters. With advice from R&D engineers, the representative similar golden dice extracted from this work are sufficient for subsequent process window analysis.
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