A new CMOS four-quadrant analogue multiplier which consists of three high speed unity-gain buffers and two NMOS transistors operated in the triode region is presented. Simulation results based on TSMC 0.6pm SPDM process parameters indicate for supply voltages of +2.5V, the linearity error can be kept below 5% for a differential input voltage range up to +1V. Total harmonic distortion at IOMHz with a 1V (peak) input signal at either input terminal with a +1V DC voltage at the other terminal is less than 5%. The simulated -3dB bandwidth of this multiplier is about 230MHz.
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