The present invention is directed to a multi-mode crystal oscillator System Selectively configurable to minimize power consumption or noise generation. Such a System is particularly applicable to the communication System of an implantable device, e.g., the microStimulator/sensor device described in U.S. Pat. Nos. 6,164,284 and 6,185,452. In Such devices, their small size limits the size of the battery contained within and thus makes it essential to minimize power consumption. Additionally, the Small size and battery capacity result in a limited transmission power. Furthermore, the Small size limits the antenna efficiency which makes it desirable to limit any noise generation to maximize the Signal-to-noise level of the resulting receive Signal. Accordingly, embodiments of the present invention alterna tively Supply power to the oscillator in either a first mode that minimizes power consumption or a Second mode that minimizes noise generation.
ALTHOUGH ANALOG CIRCUITS are usually not a major fattor in most ASICs, their design time and cost is very important. To reduce this design effort, analog standard cell libraries can be used. However, these libraries do not offer an optimum solution for every application and they become obsolete very rapidly due to tcchnology evolution.An analog design expert system has been developed t o generate device dimensions and bias currents o f a library of analog schematics (D-well and S-well CMOS) as a function of technology and desired specifications. The program also generates a complete data sheet. The basic library includes 1 2 transconductance amplifiers, 4 operational amplifiers, 3 low-noise BIMOS amplifiers, 5 voltage references, 1 quartz oscillator and 2 oversampling A/D converters including a digital decimation filter.The program is based on an accurate modeling of the devices over a wide range of bias conditions, a careful selection of the circuit diagrams and an indepth analytic description of the circuit behavior. It is interactive and allows a hierarchical design style. A flow chart of the program is given in Figure 1.which are basically healthy arc included in the library. For instance, voltage references, which make use of lateral bipolar transistors, are insensitive to the variations of 01 and p current gains of these devices'. Another example is given in Figure 2.The gain of the low noise BIMOS amplifiers is set by a resistor ratio and l/f noise is kept low by eliminating thr use of " I S transistors in the input stage.In the past, it has been shown that typical circuit behavior can easily be predicted. In our program, a worst case synthesis is performed. Taken into account are process, temperaturr and supply variations. In Figurr 3, the measured data of a voltage reference is compared with the values predicted by the program. It will be noted that even the temperature behavior can be predicted.To obtain short design time. three types of expert knowledge are employed in the program:( a t General circuit knowledge; designing cascode transistors,To be able to generate robust analog circuits only procedures obtaining a spccificd l / f noisc level with a minimum of silicon area, etc. ( b ) -Common building block knowledge; stabilizing an(c)-Specific circuit knowledge. The complexity of the used device models is also continuously adapted to the problems necded to be solved. I he program also orients the designer. For instance, for the voltage references the program tells the user how to improve his circuit performance. In the case no solution is found, the program tells why; supply voltage too low, threshold voltage too high, inadequate device performance (noise, linrarity, matching, etc.The hierarchical design style is necessary for the A/D converters. The user has t o specify his desired converter applications as well as boundaries for the performance of the usrd blocks (reference, comparator, digital filter, SC-integrator). Starting from these specifications, the program calculates all required sub-circui...
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