Despite the parsing power of LR/LALR algorithms, e.g. YACC, programmers often choose to write recursive‐descent parsers by hand to obtain increased flexibility, better error handling, and ease of debugging. We introduce ANTLR, a public‐domain parser generator that combines the flexibility of hand‐coded parsing with the convenience of a parser generator, which is a component of PCCTS. ANTLR has many features that make it easier to use than other language tools. Most important, ANTLR provides predicates which let the programmer systematically direct the parse via arbitrary expressions using semantic and syntactic context; in practice, the use of predicates eliminates the need to hand‐tweak the ANTLR output, even for difficult parsing problems. ANTLR also integrates the description of lexical and syntactic analysis, accepts LL(k) grammars for k > 1 with extended BNF notation, and can automatically generate abstract syntax trees. ANTLR is widely used, with over 1000 registered industrial and academic users in 37 countries. It has been ported to many popular systems such as the PC, Macintosh, and a variety of UNIX platforms; a commercial C++ front‐end has been developed as a result of one of our industrial collaborations.

Most language translation problems can be solved with existing LALR(1) or LL(k) language tools; e.g., YACC [Joh78] or ANTLR [PDC92]. However, there are language constructs that defy almost all parsing strategy commonly in use. Some of these constructs cannot be parsed without semantics, such as symbol table information, and some cannot be properly recognized without first examining the entire construct, that is we need "infinite lookahead." In this paper, we introduce a new LL(k) parser strategy, pred-LL(k), that uses semantic or syntactic predicates to recognize language constructs when normal deterministic LL(k) parsing breaks down. Semantic predicates indicate the semantic validity of applying a production; syntactic predicates are grammar fragments that describe a syntactic context that must be satisfied before application of an associated production is authorized. Throughout, we discuss the implementation of predicates in ANTLR-the parser generator of The Purdue Compiler-Construction Tool Set.

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Linking is traditionally a batch process that resolves cross-references between object modules and run-time libraries to produce a stand-alone executable image. Because most program changes only involve a emall part of the program, we have implemented an incremental linker, named Inclink, that processes only the changed modules. Inclink generates a new executable in time proportional to the size of a change; in contrast, a batch linker generates an executable in time proportional to the size of the program. To minimize updates to the executable, Inclink allocates extra space for every module. By allocating 24 percent more space in the executable for overflows, Inclink can update a module in place over 97 percent of the time. Measurements show that Inclink is more than an order of magnitude faster than the UNIXW [2] batch linker and that 88 percent of all links will take less than 2 s of CPU time on a MicroVAX-2, independent of program size.

Cache miss rates are quoted for a specific program, cache configuration, and input set; the effect of program layout on the miss rate has largely been ignored. We examine the variation of the miss rate resulting from randomly chosen layouts, the miss variation, for several cache configurations (cache size, lines size, and set-associativity), input sets, and optimization levels for five programs in the SPEC benchmark suite. We observed miss rates that varied from 0.6m to 1.8m, where m is the mean miss rate. We did not observe any consistently good layout:; across different parameters; in contrast, several layouts were consistently bad. Overall, cache line size has little effect on the miss variation, while increasing the cache size (decreasing the miss rate), decreasing the set-assaciativity, or increasing the optimization level increased the miss variation. We question the validity of using a single layout to represent the miss rate of a given program for a directmapped cache.

To evaluate the performance of a memory system, computer architects must determine the miss rate m of a cache C when running program P. Typically, the measured miss rate depends on the specific address mapping M of P set arbitrarily by the compiler and linker. In this paper, we remove the effect of the address-mapping on the miss rate by analyzing a symbolic trace T of basic blocks. By assuming each basic block has an equal probability of ending up anywhere in the address map, we determine the expected miss rate averaged over all possible address mappings.Our resulting gap model gives the expected miss rate for instruction caches of varying cache size, line size, and set associativity. Our model is simple but robust, and turns out to be the familiar LRU stack model with a statistical viewpoint. Our model allows a trace of arbitrary length to be compactly summarized in a few thousand bytes of information. Our model also predicts how an intervening trace, such as an operating system call or a task switch, will affect the miss rate. Comparisons to measured miss rates from SPEC 92 instruction traces show that our model typically has relative differences of less than 20% for a variety of cache parameters.

A b s t r a c tWe investigate the feasibility of using instruction compression at some level in a multi-level memory hierarchy to increase memory system performance. For example, compressing at main memory means that main memory and the file system would contain compressed instructions, but upstream caches would see normal uncompressed instructions. Compression effectively increases the memory size and the block size reducing the miss rate at the expense of increased access latency due to decompression delays. We present a simple compression scheme using the most frequently used symbols and evaluate it with several other compression schemes. On a SPARC processor, our scheme obtained compression rirtio of 150% for most programs.We analytically evaluate the impact of compression on the average memory access (ime for various memory systems and compression approaches. Our results show that feasibility of using compression is sensitive to the miss rates and miss penalties at the point of compression and to a lesser extent the amount of compression possible. For high performance workstations of today, compression already shows promise; as miss penalties increase in future, compression will only become more feasible.

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