Bayesian inference is an effective approach for solving statistical learning problems, especially with uncertainty and incompleteness. However, Bayesian inference is a computingintensive task whose efficiency is physically limited by the bottlenecks of conventional computing platforms. In this work, a spintronics based stochastic computing approach is proposed for efficient Bayesian inference. The inherent stochastic switching behaviors of spintronic devices are exploited to build stochastic bitstream generator (SBG) for stochastic computing with hybrid CMOS/MTJ circuits design. Aiming to improve the inference efficiency, an SBG sharing strategy is leveraged to reduce the required SBG array scale by integrating a switch network between SBG array and stochastic computing logic. A deviceto-architecture level framework is proposed to evaluate the performance of spintronics based Bayesian inference system (SPINBIS). Experimental results on data fusion applications have shown that SPINBIS could improve the energy efficiency about 12× than MTJ-based approach with 45% design area overhead and about 26× than FPGA-based approach.
Simultaneous Localization and Mapping (SLAM) is a critical task for autonomous navigation. However, due to the computational complexity of SLAM algorithms, it is very difficult to achieve realtime implementation on low-power platforms. We propose an energyefficient architecture for real-time ORB (Oriented-FAST and Rotated-BRIEF) based visual SLAM system by accelerating the most timeconsuming stages of feature extraction and matching on FPGA platform. Moreover, the original ORB descriptor pattern is reformed as a rotational symmetric manner which is much more hardware friendly. Optimizations including rescheduling and parallelizing are further utilized to improve the throughput and reduce the memory footprint. Compared with Intel i7 and ARM Cortex-A9 CPUs on TUM dataset, our FPGA realization achieves up to 3× and 31× frame rate improvement, as well as up to 71× and 25× energy efficiency improvement, respectively.
The diamagnetic levitation technique can be applied in non-destructive testing for identifying cracks and defects in magnetic materials. Pyrolytic graphite is a material that can be leveraged in micromachines due to its no-power diamagnetic levitation on a permanent magnet (PM) array. However, the damping force applied to pyrolytic graphite prevents it from maintaining continuous motion along the PM array. This study investigated the diamagnetic levitation process of pyrolytic graphite on a permanent magnet array from various aspects and drew several important conclusions. Firstly, the intersection points on the permanent magnet array had the lowest potential energy and validated the stable levitation of pyrolytic graphite on these points. Secondly, the force exerted on the pyrolytic graphite during in-plane motion was at the micronewton level. The magnitude of the in-plane force and the stable time of the pyrolytic graphite were related to the size ratio between it and the PM. During the fixed-axis rotation process, the friction coefficient and friction force decreased as the rotational speed decreased. Smaller-sized pyrolytic graphite can be used for magnetic detection, precise positioning and other microdevices. The diamagnetic levitation of pyrolytic graphite can also be used for detecting cracks and defects in magnetic materials. We hope this technique will be used in crack detection, magnetic detection and other micromachines.
Bayesian method is capable of capturing real world uncertainties/incompleteness and properly addressing the overfitting issue faced by deep neural networks. In recent years, Bayesian Neural Networks (BNNs) have drawn tremendous attentions of AI researchers and proved to be successful in many applications. However, the required high computation complexity makes BNNs difficult to be deployed in computing systems with limited power budget. In this paper, an efficient BNN inference flow is proposed to reduce the computation cost then is evaluated by means of both software and hardware implementations. A feature decomposition and memorization (DM) strategy is utilized to reform the BNN inference flow in a reduced manner. About half of the computations could be eliminated compared to the traditional approach that has been proved by theoretical analysis and software validations. Subsequently, in order to resolve the hardware resource limitations, a memory-friendly computing framework is further deployed to reduce the memory overhead introduced by DM strategy. Finally, we implement our approach in Verilog and synthesise it with 45 nm FreePDK technology. Hardware simulation results on multi-layer BNNs demonstrate that, when compared with the traditional BNN inference method, it provides an energy consumption reduction of 73% and a 4× speedup at the expense of 14% area overhead.
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