In this paper, two versions of capacitive accelerometers based on low-temperature co-fired ceramic (LTCC) technology are developed, different with respect to the detection technique, as well as the mechanical structure. Fabrication of the key structure, a heavy proof mass with thin beams embedded in a large cavity, which is extremely difficult for the conventional LTCC process, is successfully completed by the optimized process. The LC resonant accelerometer, using coupling resonance frequency sensing which is first applied to LTCC accelerometer and may facilitate application in harsh environments, demonstrates a sensitivity of 375 KHz/g over the full scale range 1 g, with nonlinearity less than 6%, and the telemetry distance is 5 mm. The differential capacitive accelerometer adopting differential capacitive sensing presents a larger full scale range 10 g and lower nonlinearity less than 1%, and the sensitivity is 30.27 mV/g.

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With the technology nodes keep advancing, the application of TSV(Through Silicon Via) technology in 3D integration is faced with more challenges. The shift from via-last to via-middle fabrication scheme, the ever-increasing density of TSV, the reduction in supply voltage and the increase in frequency of on-chip local clock, all pose threat to signal/power integrity of the TSV system. In this paper, the noise coupling effect between TSVs and corresponding suppression methods were modeled and analyzed. Effect of variations of structural parameters on noise coupling are investigated and results are explained based on specifications of advanced technology node. In order to alleviate noise effect under fine pitch scenario, different noise suppression methods are discussed and compared. The guard-ring didn't demonstrate much noise reduction over the whole frequency spectrum, with slightly better performance within the low frequency range. The buried oxide layer of SOI technology also showed little suppression effect in blocking substrate noise. However, the TSV array scheme is significantly effective in noise suppression over the whole frequency spectrum.

Three potential contributing factors to the TSV leakage and breakdown are discussed and analyzed in this study. In addition, an in-line testing methodology is put forward so that leakage and breakdown data could be easily obtained. Finite element method simulation was used to illustrate the testing principle, and experimental test were carried out for validation. It was found that the most contributing factor to the TSV leakage and breakdown is the uniformity of the insulator layer thickness, while via-diameter and pitch between TSVs are factors of failure mechanism of the low-frequency characteristics.

In this study, a stacked SRAM module with a built-in decoder was proposed with a through-multilayer TSV integration process. The through-multilayer TSVs provided data passages for all common signals, including the address bus, data bus, power, read and write control, which were redistributed at each individual chip, while the chip select signals were connected separately to the built-in decoder. Regarding this process, a novel double-layer spin coating technology was employed to prevent photoresist residue left inside TSVs, and the RDLs in this process could be fabricated using lift-off process prior to via filling. As a result, the front side CMP process was not necessary. A 10-layer throughmultilayer TSV integration sample was successfully fabricated with this process. Preliminary testing results suggested that this process was promising for integration of memory chips with similar layout. Background3D integration using through silicon via (TSV) has many advantages, such as high packaging density, small form factor and high bandwidth due to the short connection lengths [1-3]. 3D memory chip module is one of the promising 3D-TSV integration applications, which can largely reduce the chip area and is helpful to performance improvement and cost reduction [4], [5]. Recently, variety of 3D-TSV integration approaches for 3D memory module, including DRAM and NAND Flash, has been reported [6-10]. In a 3D memory module, most I/O signals of a memory chip, including address bus, data bus, power, read and write control, are common signals, and could be shared with other memory chips in the module. Considering of this feature of 3D memory module, in this paper, we have proposed a simplified through-multilayer TSV integration process aiming at stacked SRAM module. A stacked SRAM module has been designed using commercial 2D EDA tools, which simplified the complexity of 3D module design, meanwhile took the technical advantages of 3D integration. The feature of this TSV integration process was RDL formation prior to TSV filling. Thus front side planarization by CMP (Chemical Mechanical Polishing) process after TSV filling was not necessary. With this process, a 10-layer TSV integration sample was successfully fabricated.