In high-speed applications, MOS current mode logic (MCML) is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP). However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML) circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.
Scaling supply voltage is an efficient technique to achieve low power-delay product. This study presents low-power Single-Rail MOS Current Mode Logic (SRMCML) circuits which operate on near-threshold region. The near-threshold operations for the basic SRMCML circuits such as inverter/buffer, OR2/NOR2 and 2/NAND2, OR3/NOR3 and XOR3/NXOR3 are investigated. All circuits are simulated with HSPICE at the SMIC 130 nm CMOS process by varying supply voltage from 0.6V to 1.3V with 0.1V steps. Based on the simulation results, lowering supply voltage is advantageous. The power dissipations of the proposed near-threshold SRMCML basic gates are almost the same as the conventional Dual-Rail MCML (DRMCML) circuits and the delay of the SRMCML is less than the DRMCML because of its single-rail scheme.
MOS Current-Mode Logic (MCML) is usually used for high-speed applications. However, almost all MCML circuits are realized with dual-rail scheme. The dual-rail logic circuits increase extra area overhead and the complexity of the layout place and route. Moreover, little standard cells of the dualrail logic circuits have been developed for place-and-route tools, such as Cadence Encounter. In this paper, a single-rail scheme of MCML circuits is proposed. The design methods of the basic single-rail MOS Current-Mode Logic (SRMCML) circuits are presented, such as inverter/buffer, OR2/NOR2, AND2/NAND2, OR3/NOR3, and 1-bit full adder. All circuits are simulated with HSPICE at the SMIC 130 nm CMOS process. The power dissipations of the basic SRMCML cells are compared with the conventional dual-rail MCML ones. The power dissipation of the proposed SDMCML circuits is almost the same as the conventional dual-rail ones. The SRMCML circuit can attain smaller powerdelay product than dual-rail MCML ones because of its single-rail scheme.
Abstract:In this paper, a power-gating technology for single-rail MOS Current Mode Logic (SRMCML) circuits is presented, which use the high-threshold PMOS transistors as linear load resistors to reduce the power dissipation in the sleep mode. The basic SRMCML cells, such as buffer/inverter, AND2/NAND2, AND3/NAND3, OR2/NOR2, OR3/NOR3, XOR2/XNOR2, multiplexer, and 1-bit full adder, are used to verify the effectiveness of the proposed power-gating scheme. The equivalent model for calculating energy dissipations of the power-gating SRMCML circuits is constructed. All circuits are simulated with HSPICE at a 130 nm CMOS process. By simulating power-gating SRMCML circuits in active and sleep modes, it is concluded that the power dissipation of power-gating SRMCML circuits in sleep mode is reduced with the decrease of the device sizes of high-threshold PMOS sleep transistors, while the power dissipation of power-gating SRMCML circuits is almost independent of the device sizes of sleep transistors in active mode. The power dissipation comparisons among power-gating SRMCML, conventional SRMCML, and power-gating static CMOS circuits are carried out. The power dissipation of the proposed power-gating SRMCML circuits is the least among the three above mentioned structures.
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