This paper presents the design and measurement results of two avalanche photodiode structures (APDs) and a novel frequency-mixing transimpedance amplifier (TIA), which are key building blocks towards a monolithically integrated optical sensor front end for near-infrared (NIR) spectroscopy applications. Two different APD structures are fabricated in an unmodified 0.18 \im CMOS process, one with a shallow trench isolation (STI) guard ring and the other with a P-well guard ring. The APDs are characterized in linear mode. The STI bounded APD demonstrates better performance and exhibits 3.78 A/W responsivity at a wavelength of 690 nm and bias voltage of 10.55 V. The frequency-mixing TIA (FM-TIA) employs a T-feedback network incorporating gate-controlled transistors for resistance modulation, enabling the simultaneous down-conversion and amplification of the high frequency modulated photodiode (PD) current. The TIA achieves 92 dS Ω conversion gain with 0.5 V modulating voltage. The measured IIP(3) is 10.6/M. The amplifier together with the 50 Ω output buffer draws 23 mA from a1.8 V power supply.
This paper presents design and measurement results of a fully integrated optical sensor for phase and amplitude detection of RF modulated optical signals up to 110 MHz in the near-infrared (NIR) region (650-850 nm) for use in frequency-domain spectroscopy instruments. The sensor consists of an NIR-sensitive photodetector monolithically integrated with a front-end analog amplifier and signal processing circuitry for amplitude and phase detection in an unmodified complementary metal oxide semiconductor (CMOS) process. A high-gain, low-noise differential transimpedance amplifier (TIA) is implemented to amplify the photocurrent signal. Amplitude and phase resolution are evaluated with a 690 nm laser diode modulated at 100 MHz. The amplitude response exhibits 2.2 mV Wresolutionwith0.4%linearity.The measured amplitude output noise is 72 V. The proposed phase detector detects 0 -360 phase difference with a measured average phase resolution of 4.8 mV/degree and 255 V output noise. The sensor is implemented in a 180 nm CMOS technology and consumes 23.4 mW from a 1.8 V supply voltage.
A least mean square (LMS) based calibration algorithm is proposed to calibrate most known error sources in 1.5 bit/stage pipelined ADCs, known to be immune to moderate comparator offsets. The error sources include linear gain errors, reference voltage errors, systematic offset errors and amplifier non-linear errors of each pipeline stage. LMS is used to estimate the error parameters in the digital domain. After estimation the proposed algorithm calibrate the pipelined ADC using the estimated parameter errors. Simulation results show that the proposed algorithm can improve the ENOB from 6.6 bits to 13.9 bits for a 14 bit 1.5 bits/stage pipelined ADC.
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