The advanced microprocessors are widely used for most of the complex systems. A silicon chip of fingernail-size may exhibit entire high performance guaranteed processor, higher cache memory and logic needed for interfacing with external devices. Reduced Instruction Set Computing (RISC) is a CPU (Central Processing Unit) design mechanism based on the vision in which exhibits basic instruction set and yields better performance after comparison with microprocessor architecture and it has the capacity to perform the instructions through microprocessor cycles per instruction. In this paper, the Cost-effective and efficient RISC Processor is designed. The RISC Processor design includes Fetching, decoding, Data and instruction memory, and Execution units. The Execution unit contains ALU (Arthematic and Logical Unit) Operations. The RISC Processor design is synthesized and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The implementation is done by Artix-7 FPGA device and the physically debugging of the RISC Processor, and ALU Units are verified using Chipscope pro tool. The performance results are analyzed in terms of the Area (Slices, LUT's), Timing period, and Maximum operating frequency. The comparison of the RISC Processor is made concerning previous similar architecture with improvements.
Today every circuit has to face the power consumption issue for both portable device aiming at large battery life and high end circuits avoiding cooling packages and reliability issues that are too complex. It is generally accepted that during logic synthesis power tracks which works well with area. This means that a larger design will generally consume more power. The multiplier is an important kernel of digital signal processors. Because of the circuit complexity, the power consumption and area are the two important design considerations of the multiplier. In this paper a High Speed & low area architecture for the shift and add multiplier is proposed. The simulation result for 8 bit multipliers & four tap Filters shows that the proposed Low Area & Delay architecture lowers the total Area & Delay when compared to the Array Multiplier and Booth Multiplier architecture based Filter. To develop the system blocks in Modelsim 6.4a and Xilinx ISE9.1i, the Spartan3 FPGA tool is used which achieves the simulation and the synthesis of the proposed multiplier. Verilog HDL is the language used for designing the proposed multiplier.
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