For drone vision and navigation, low-power 1 3-D depth sensing with robust operations against strong/weak 2 light and various weather conditions is crucial. CMOS image 3 sensor (CIS) and light detection and ranging (LiDAR) can 4 provide high-fidelity imaging. However, CIS lacks depth 5 sensing and has difficulty in low light conditions. LiDAR is 6 expensive with issues of dealing with strong direct interference 7 sources. Ultrasound imaging system (UIS), on the other hand, 8 is robust in various weather and light conditions and is 9 cost-effective. However, in air channel, it often suffers from long 10 image reconstruction latency and low framerate. To address 11 these issues, we present a UIS application-specific integrated 12 circuit (ASIC) that adopts the one-shot transmitter (TX) and 13 on-chip per-voxel receiver (RX) beamfocusing (PV-RXBF) 14 image reconstruction scheme. The ASIC adopts the designs of 15 fully differential charge-reuse high-voltage TX (FDCR-HVTX), 16 digital back-end (DBE), and an on-chip power management unit 17 (PMU). FDCR-HVTX generates 28 V pp pulses and reduces the 18 average power consumption by 25% by charge reuse (CR). The 19 DBE achieves 7.76-µs processing latency and 9.83M-FocalPoint/s 20 throughput to effectively translate real-time 3-D image streaming 21 at 24 frames/s. A prototype UIS, with an 8 × 8 bulk piezo 22 transducer array, is assembled with the proposed ASIC and 23 a wireless data transmission module [field-programmable gate 24 array (FPGA) + ESP32] on an entry-level consumer drone, 25 and the real-time wireless 3-D image streaming at 24 frames/s 26 with a range of 7 m is verified while the drone is flying.
Wide input-output (IO) chip-to-chip interfaces, such as 3-D chip stacking [through-silicon via (TSV)], silicon interposer in high-bandwidth memory (HBM), and other 2.5-D chip-to-chip interface, handle a large amount of data in the server and artificial intelligence (AI) applications. With a large number of IOs, power consumption becomes a huge burden. This article presents a novel charge recycling (CR) logic with >20% power reduction under random data streaming. The presented generic CR technique is applicable to both TSV and transmission line (T-Line) link IOs. The CR logic is implemented on two silicon dies where the single-channel CR (CR1) uses a storage capacitor to recycle charge at each data transition and multi-channel CR (CR2/4/8) replenishes the charge between multiple channels during the opposite transitions. Fabricated in a 40-nm 1P8M standard CMOS, the TSV link (2.56 Gb/s) and the T-Line link (5.12 Gb/s) save energy up to 32.2% and 47%, respectively, under periodic data transmission and up to >20% under pseudorandom binary sequence (PRBS). The eye diagrams and the bit error rate (BER) show that signal integrity is maintained when compared with conventional data links.
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