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Temperature dependent measurements have been used to examine transport mechanisms and energy band structure in MOS devices. In this study, a comparison between high-k HfO2 dielectrics and conventional SiO2 dielectrics is made to investigate dielectric specific thermally activated mechanisms. Temperature dependent measurements on large area n/pMOSFETs composed of SiO2 and HfO2/SiO2 gate dielectrics were performed from 5.6K to 300K. A large increase in the gate leakage current is observed at the formation of the minority carrier channel. The data indicate that gate leakage current prior to the formation of the minority channel is carrier rate limited while gate leakage current is tunneling rate limited above the threshold voltage. Gate leakage current measurements show two distinct Arrhenius transport regimes for both SiO2 and HfO2 gate dielectrics. The Arrhenius behavior of the gate leakage current is characterized by a strong temperature dependent regime and a weak temperature dependent regime. The activation energy of the strong temperature regime is found to vary with the applied gate voltage. Frenkel-Poole or other electric field models are able to explain the gate voltage dependence of the gate leakage current for the lowtemperature/voltage regime investigated. The data suggest that the variation of the activation energy for the Arrhenius behavior is weakly electric-field driven and strongly voltage, or Fermi energy level, driven. The weak electric field and strong voltage dependence of the thermal characteristics of the gate leakage current may point to trap densities within the HfO2 that vary in energy (hence applied voltage) as responsible for the observed activation energies. Trap assisted tunneling (or hopping) could be implicated as the transport mechanism.

This paper presents a study of the variation of the piezoresistive coefficients over several devices on the same die, the same wafer, and finally at different doping levels. The sensor test vehicles are fully documented, and a thorough error analysis on the method of applying a known uniaxial state of stress is presented. The results show that individual stress sensor calibration is required if the uncertainty in the absolute values of the measured stresses need to be less than 15%. If the uncertainty only needs to be less than 50% then one device per wafer can be calibrated, or an equation relating the unstressed resistance values to the piezoresistive coefficients can be used. Piezoresistive Coefficient Variation StudvAlthough the study of the piezoresistive effect in silicon has been investigated for some time now, the variation of the piezoresistive coefficients associated with piezoresistive-based integrated circuit stress sensors has not yet been addressed with any great certainty in the literature. The motivation for a thorough understanding of these coefficients and their variation with doping density, dopant type, temperature, and other physical parameters, is driven by the present need to individually calibrate the sensors to obtain accurate stress measurements [51[61[71[81[91. Present stress sensing chips designed to measure the distribution of a single stress component over a die can contain over twenty resistors [lo], each of which needs calibration to assure accuracy of subsequent stress measurements. This number of resistors can further increase if it is desired to measure biaxial or triaxial stress states at each point of interest. This places an excessive burden on the calibration process if enough stress sensing chips are to be obtained to be able to qualify a process sequence or packaging technology.In order to determine the number of calibrations required for a specific error tolerance, an analysis of the piezoresistive coefficient variation over many devices is required. If it is found that the coefficients vary only a small percentage over an entire wafer, then one calibration step could suffice for that entire wafer. If the coefficients vary only slightly from wafer to wafer then possibly one device per lot could suffice for the calibration needs. Understanding these variations of the coefficients is essential to determining the calibration requirements of a specific application.The following sections of this paper address the observed variations of the calibrated piezoresistive coefficients versus doping density as well as quantifying the experimental error associated with the four-point bend (4PB) stress fixture used in the calibration experiments.

Electrical bitmapping and physical failure analysis were used to detect a small silicide break within a memory circuit which led to severe yield loss on our 0.20 p i CMOS process. A parallel, two-phase approach was used to optinzize the titanium silicide formation process and the silicon suYface preparation prior to titanium silicide. Several process and mask tooling modifications were implemented as a result of these efforts, which led to added robustness of the silicide process module and dramatic increases in wafer probe yield.