A digital negative phase shifter circuit is present to provide negative delays (phase shift) in order to avoid multi-locking hazards. It can adjust the negative phase by using multiplexers and voltage variable delay cells to select the required phase shift. The design is implemented by 0.35 £ m CMOS 1P4M technology. A single-shot locking method is adopted to reduce the locking time. Most important of all, the negative phase shift is predictable and adjustable. The simulation results show that the accuracy of the proposed design is better than 6%.
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