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In this paper, the charge trapping and decay mechanism is investigated in post deposition rapid thermal anneal (RTA) and furnace anneal (FA) erbium oxide (Er 2 O 3 ) ultrathin films by Kelvin probe force microscopy (KPFM) technology. The trap density is calculated by the contact potential difference measurements obtained from KPFM. Furthermore, it is compared with the trap density calculated from the electrical measurements for Er 2 O 3 MOS capacitors to give an insight on the reliability of KPFM for trap density estimation. Experimental results showed that post deposition RTA treatment results in higher trapping as compared to FA treatment on Er 2 O 3 ultrathin films. It was observed that vertical charge leakage plays a dominant role in Er 2 O 3 as compared to lateral charge spreading. The space-charge-limited conduction mechanism was observed in Er 2 O 3 MOS capacitors, which was used to study the charge injection and decay mechanism. This investigation may help to fill the trap density computation gaps between nanoscopic KPFM and macroscopic capacitance-voltage-based electrical measurements for nanoscale MOS-based applications.Index Terms-Charge trapping, high-κ, rare earth oxides (Er 2 O 3 ), rapid thermal annealing (RTA), Kelvin probe force microscopy (KPFM), MOS.

Over the decades since ferroelectricity was revealed, ferroelectric materials have emerged as a cornerstone for a wide spectrum of semiconductor technology and electronic device applications, particularly in state-of-the-art complementary metal oxide semiconductor (CMOS) logic circuits and digital information storage media. Recent unprecedented advancements and future perspectives on integrating ferroelectric materials, particularly with high-κ dielectrics for electronic devices, are weighed. The emphasis is on (i) application (logic and memory); (ii) ferroelectric materials (organic, inorganic, and two-dimensional (2D)); (iii) device structures (metal/ferroelectric/metal (MFM), metal/ferroelectric/semiconductor (MFS), metal/ferroelectric/insulator/semiconductor (MFIS), and metal/ferroelectric/metal/insulator/semiconductor (MFMIS)); and (iv) next-generation electronic devices (negative capacitance field effect transistors (NC-FETs), ferroelectric RAM (FeRAM), ferroelectric field effect transistors (FeFETs), and ferroelectric tunnel junctions (FTJs)). In NCFETs, the ferroelectric layer serves as a negative capacitor so that the channel surface potential can be amplified more than the gate voltage. Hence, devices can overcome the “Boltzmann tyranny” and operate with a steep subthreshold swing < 60 mV/dec and supply voltage < 0.5 V. Thus, NC-FETs would be more suitable for high-speed logic operations, scalability, low-power, and cost-effectiveness, targeting applications such as 14T-type CPU registers and 6T-type cache static random access memory (SRAM). Ferroelectrics also opens a path to solving the problems associated with technology scaling due to the unique structural and electronic properties. Ferroelectric memories are anticipated to be in different flavors based on optimum performance, cost, and end-user requirements. Herein, we deliberate on the exciting possibilities for the development of device structures such as one-transistor one-capacitor (1T-1C)-type FeRAM with fast access time (<10 ns), high endurance (∼>1014 cycles), and moderate data retention being considered as a strong contender for volatile dynamic random access memory (DRAM), while, for nonvolatile memory applications, 1T-type ferroelectric gated transistors, called FeFETs with nondestructive readout, fast access time (∼<100 ns), moderate endurance (>109 cycles), and high retention time (>10 years) have the potential to compete with embedded solid-state drives (SSDs). Finally, the FTJs with three-dimensional cross-point architecture are strong contenders for high-density niche storage applications to interchange with low-cost per bit external hard disk drives. We conclude with a brief survey of recent ferroelectrics advances and potential futuristic comparisons for next-generation computing and storage device applications so the field may expand and pave the way for high-volume manufacturing of semiconductor technology down to the sub-5 nm node over the coming years.