In this paper, a method to reduce the second order effects on the circuit performances caused by the small sized MOS transistors is proposed. A current mode square-root circuit, a squarer/divider circuit and a multiplier/divider circuit are designed using this method. Proposed circuits have been simulated with SPICE simulator using 0.35 lm CMOS technology parameters. The main advantages of the proposed circuit are reduced errors of the output current function, a smaller area on the chip, possibility of controlling the output current with the control voltage, operation at higher frequencies and more efficient power consumption. As a result, it can be considered as a useful building block for IC designer.Keywords Reduction of second order effects in MOSFET's Á Square-root circuit Á Squarer/divider circuit Á Multiplier/divider circuit Á Square-root domain 1 Introduction
A new method has been proposed to reduce the mobility degradation effect on square-law characteristic of the MOS transistor. This method has been applied to an analog multiplier to form a new low distortion multiplier circuit. This analog multiplier operates with ± 5V power supply. The operating range for each input is ± 3V. In this operating range the nonlinearity for Vx is 0.6% and for Vy is 0.5%. The 3dB bandwidth is specified for Vx as 33MHz and for Vy as 34MHz, respectively. I. INTRODUCTIONAnalog multipliers are the key elements of signal processing circuits. There are several techniques of implementing four quadrant multipliers including techniques based on square-law characteristic of the MOS transistor operating in the saturation region. Several second order effects influencing the linearity of multiplier circuits are reported in the literature [1][2][3][4][5][6][7]. Mobility degradation caused by short channel effect is the most important factor which degrades the linearity of this kind of multipliers. Althought there are several analog multipler circuits [1][2][3][4][5][6][7] based on squarelaw characteristic of MOS transistor, in none of them any special precaution has been introduced to reduce the short channel effect. In this work a new method has been proposed for reducing the mobility degradation effect on square-law characteristic of the MOS transistor. This method has been applied to an analog multiplier [1] to form a new low distortion multiplier circuit. This analog multiplier operates with ± 5V power supply. The operating range for each input is ± 3V. In this operating range the nonlinearity for Vx is 0.6% and for Vy is 0.5%. The 3dB bandwidth is specified for Vx as 33MHz and for Vy as 34MHz, respectively.
Ozet~eBu 9ah~mada karekok bolgede 9ah~an dogrusal tek 9lkl~h ve dengeli 9ift 9lkl~h ge9i~iletkenligi devresi onerilmi~tir. Onerilen devreler yuksek frekanslarda 9ah~maya, kU9iik boyutlu MOS tranzistorlarla kurulmaya, standart CMOS prosesine uygun olup karekok bolgede 9ah~an siizge9 ve osilator gibi devre yaptlan i9in de kullantlabilir. Boylece bu devreler analog i~aret i~leme devrelerinin tasanmlnda yeni olanaklar saglayabilecektir. Onerilen yaptlara yonelik analizler SPICE devre benzetim progranunda, TSMC 0.35J.lm CMOS teknolojisi kullanllarak gergekle~tirilmi~tir. AbstractIn this paper, a square-root domain linear single output transconductance circuit and a balanced double output transconductance circuit are proposed. Proposed circuits are suitable for operation at high frequencies, designed with small sized transistors, standard CMOS fabrication and appropriate oscillator design and filtering in square-root domain. Thus, these circuits provide new possibilities in the design of analog signal processing circuits. The proposed circuits which have been simulated with SPICE simulator in TSMC O.35J.lm CMOS technology.MOS tranzistorun gerilim-akim ili~kisinin karesellikten lineerlige dogru degi~tigi ve bu sebeple klsa kanalh tranzistorlarla kurulan devrelerin 91kl~fonksiyonlannda hatalarln olu~tugu bilinmektedir. Bu probleme yonelik yapllan bir90k ara~t1rma sonucunda yuksek dogruluklu karekok ahcI ve kare-ahctlboliicii devreler onerilmi~, bu devrelerin kullantlmaslyla karekok bolgede 9ah~an devreler tasarlanml~t1r [7][8][9][10][11][12].Bu 9ah~mada onceden literatiire sunulmu~olan yiiksek dogruluklu karekok ahcI devreden [7] yararlantlarak, karekok bolgede 9ah~an dogrusal tek 9lkl~h ve dengeli 9ift 9lkl~h ge9i~iletkenligi devreleri onerilmi~tir. Onerilen yaptlara yonelik analizler SPICE devre benzetim programlnda, TSMC 0.35J.lm CMOS teknolojisi kullantlarak gergekle~tirilmi~tir. Onerilen devrelerin egimi kontrol aklml ve kontrol gerilimiyle degi~tirilebilmektedir. Kisa kanal etkilerini azaltan yontem sayesinde devreleri olu~turan tranzistorlann boyutlan olduk9a kU9uk ahnabilmekte, devreler emsallerine gore 90k daha kii9Uk boyutlarda uretilebilecek~ekilde tasarlanabilmekte ve kU9iilen boyutlar nedeniyle daha yiiksek frekanslarda 9ah~abilme olanaglna da sahip olunmaktadlr. Kii9iik boyutlarda tasarlanabilmeleri, kontrol aktm ve gerilimiyle egimin ve dolaylslyla 91kl~fonksiyonlarlnln kontroI edilebilmesi, yuksek frekanslarda 9ah~abilmeleri ve dii~iik gii9 kullanlml onerilen devrelerin ba~hca avantajlarl olarak slralanabilir.
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