Multi-level-cell (MLC) flash memory comprises of cells whichcan be programmed to multiple levels. Recent MLC flash memory systems support 3 bits per cell to 4 bits per cell which means that the individual cells are programmed to 8 or 16 distinct levels respectively. MLC flash has higher raw bit error rate (rber) than the single bit per cell flash. This calls for the use of sophisticated error control coding (ECC) schemes like LDPC codes. The flash memory channel is usually modeled with level distributions having Gaussian probability density function. However, the Gaussian distribution is not a good fit for practical NAND channels. Even for the beginning of life of the flash memory device, this model has to be replaced by a more realistic model. With erases and re-writes, the channel towards the end of life of the device is far from Gaussian and floating-gate to floating-gate coupling and charge loss not only increases the raw bit error rate but causes the level distributions to become asymmetric. Given such channel impairments, if the LDPC decoder assumes Gaussian level distributions, its performance can degrade considerably. Hence, modifications are required in the decoding algorithm to cope up with the channel distortions. In order to keep the hardware costs within limits, simple schemes with minimal hardware increase are desirable to keep up the performance. In this paper, the flash channel degradations are first enlisted and then simple solutions are proposed which keep the performance in check as the flash memory transits from a channel with moderate impairments to the end of life condition, where the level distributions for the different levels are highly asymmetric.
For NAND Flash memory, a read comprises reading the word line at a particular read reference voltage. The read reference voltage is critical as it determines the bit error rate. For equi-probable levels, the optimum read reference is at the intersection of the level probability density functions. In this paper, we propose two methods to obtain the optimum read reference voltage. The first method comprises estimating the parameters of the level's cumulative distribution function. Knowledge of the parameters can then be used to obtain the optimum read reference voltage. In order to estimate the parameters, multiple reads from the Flash memory have to be performed. For latency considerations, we are constrained by the number of allowed reads and want to minimize them. The reads from the Flash memory coupled with the error correcting code output are used to obtain the distribution values. This method involves computing the inverse of the cumulative distribution function to obtain the mean and variance of the distributions. The inverse of the cumulative distribution function is highly sensitive to the measurement noise. Hence, this method needs more reads to mitigate the effects of the measurement noise. The second method consists of using bounded functions based on polynomials to interpolate the cumulative distribution function between the measured values and extrapolate it beyond. This method is more robust to measurement noise.We performed simulations using real Flash memory data to validate the algorithms. The distribution fits we obtain are very close to the actual histograms in the tail region of the distributions. This leads to obtaining bit error rates close to optimum. We extend the method developed for single level cell case to the multi level cell Flash memory, with the upper page read accompanied by the lower page read. In further extensions, we make use of the knowledge of channel impairments and the variance of the distribution over cycles to estimate the cumulative distribution function for the case of only one read from the Flash memory. Simulation results show one order of improvement in the bit error rate using these algorithms.
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