Automation is a technology in that there are different kind of approaches and procedures can be referred. The process of turning manual checks to automatic checks provides impressive benefits. Time saving, cost effective, higher quality, accurate result, less error in the tests which normally caused by human are the most important reasons to thinking about automation. The first and foremost step is to find out what should be automated. It is important to know the reason of automation if, it is worth or not. Here, the question is based on which reason it should decide for automation? For instance, after finishing all the runs of Innovus, Voltus, Pegasus, Quantus top level person must verify that whether it is meeting the specifications or not for checking that they need to go through all the audit files. Audit files doesn’t contain detailed information’s like incremental tag, tool version, time stamp, md5sum’s, waivable warnings, must fix warnings, must fix errors, input directory paths, Bump locations and VDD and VSS locations etc. and other factor is Time consuming.By doing automation it will gives required detailed information like latest incremental tag and tool version, md5sum its unique id, time stamp, errors, warnings, setup and hold views etc. so it can be automated by developing script using programming language called TCL (tool command language). These scripts will work for any block of a chip which is of 16nm technology.
VLSI industry has been rapidly growing where multiple processors can be implemented on a single chip. In physical design of a chip main factors to be considered are timing closure, congestion, and power. Compare to 180nm and 90nm designs were not much complicated due to less transistor density as going to lower technology nodes chip size, area, length will decrease that impact on packaging and cooling issues, so it is necessary to estimate the power at the early stage of design. Power analysis is done immediately after placement and routing stage of the chip. Power analysis can be performed in two methods one is flat method and other is hierarchical method. In flat method of analysis, the data of both top level and block level is given as input data to calculate the results whereas in hierarchical method of analysis the Power Grid View (PGV) of hierarchical block is designed which is then given as input. In hierarchical runs the sub-blocks are black boxed. The simulation is carried out using the Voltus IC Integrity Solution tool from cadence for a chip designed in 16nm FinFET technology. The results obtained from the flat method of analysis takes 2X the runtime compared to hierarchical method which would be unfavorable for very much larger circuits. The IR drop in VDD and VSS are 11.69 mW and 11.02mW respectively in flat method and 12.32 mW and 13.26 mW for VDD and VSS in hierarchical method of analysis. The accuracy is more obtained in flat run due to its transparency in logic functions.
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