In this paper, we present an analog hierarchical sizing methodology applied to a third-order charge pump phase-locked loop (CPPLL). The key idea is to propagate the specifications from the requirements of the behavioral level to the circuit level. At the behavioral level, the performance is optimized while considering the potential capacity of the underlying circuits. Critical advantage of the illustrated methodology is a shortened PLL sizing process due to the use of fast-simulating models at behavioral level. The simulation results show the availability of this method on the CPPLL which makes an automatic sizing process actually feasible in terms of computation time.
In the last few years, several Low Temperature Cofired Ceramics (LTCC) materials with a silicon adapted Coefficient of Thermal Expansion (CTE) have been developed for direct wafer bonding to silicon. BGK (special type designation of Fraunhofer IKTS), a sodium containing LTCC was originally developed for anodic bonding of the sintered LTCC whereas BCT (Bondable Ceramic Tape) tailored for direct silicon bonding of green LTCC tapes to fabricate a quasi-monolithic silicon ceramic compound substrate. This so-called SiCer technique is based on homogeneous nano-structuring of a silicon substrate, a lamination step of BCT and silicon and a subsequent pressure assisted sintering. We present a new approach for an integrated RF-platform-setup combining passive, active and mechanical elements on one SiCer substrate. In this context RF parameters of the silicon adapted LTCC tapes are investigated. We show first technological results of creating cavities at the silicon ceramic interface for SiCer-specific contacting options as well as windows in the ceramic layer of the SiCer substrate for additional silicon processing. A further investigated platform technology is deep reactive ion etching of the silicon-ceramic-composite-substrate. The etching behavior of silicon on BCT will be demonstrated and discussed. With the SiCer technique it is possible to reduce the silicon content at the setup of RF MEMS to a minimum (low signal damping).
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