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In this brief, we show that forward error correction (FEC) can reduce power in high-speed serial links. This is achieved by trading off the FEC coding gain with specifications on transmit swing, analog-to-digital converter (ADC) precision, jitter tolerance, receive amplification, and by enabling higher signal constellations. For a 20-in FR4 link carrying 10-Gb/s data, we demonstrate: 1) an 18-mW/Gb/s savings in the ADC; 2) a 1-mW/Gb/s reduction in transmit driver power; 3) up to 6× improvement in transmit jitter tolerance; and 4) a 25-to 40-mV improvement in comparator offset tolerance with 3× smaller swing.

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In this paper, we look at how the introduction of Forward Error Correction (FEC) impacts system design in a high-speed I/O link. We present examples where coding gain maps to improvements in transmit swing, ADC precision, jitter tolerance and comparator offset tolerance.

This paper presents the architecture of a non-uniform reference level bit error-rate (BER)-optimal analog-to-digital converter (ADC) and equalizer, for high-speed communication links. Finite precision analysis demonstrates that the use of the BER-optimal ADC does not increase the equalizer complexity/power significantly. An adaptive algorithm referred to as the approximate minimum BER algorithm (AMBER) is proposed in order to determine the BER-optimal reference levels. Finite-precision analysis of AMBER indicates that reference levels represented with 9-bit precision is sufficient for a 3-bit BER-optimal ADC to achieve BER equal to that of a 4-bit conventional ADC. An architectural implementation of AMBER is also presented. The reference-level adaptation unit (RL-UD) has a full-adder (FA) complexity that is 76% over the conventional adaptive equalizer. The RL-UD block is clock-gated after convergence and hence does not present a power overhead. Thus, for high-speed links employing the flash ADC architecture, the proposed AMBER receiver represents a power savings of approximately 50% in the ADC.

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This paper presents the first reported design of a forward error correction (FEC)-based high-speed serial link. A 4 Gb/s line rate transceiver in 90nm CMOS is designed with short block length BCH codes. FEC is shown to be effective for high code rates, high information rates and low SNR channels. Measurement results of the transceiver over a 18.2 dB Nyquist loss channel show a reduction in minimum BER, and an increase in jitter tolerance at low transmit swings. For a BER 10 -12 , the addition of FEC reduces the required transmit signal swing, from approximately 0.75 V ppd to less than 0.5 V ppd .