The real time moving object and face detections are used for various security applications. In this paper, we propose FPGA implementation of moving object and face detection with adaptive threshold. The input images are passed through Gaussian filter. The 2D-DWT is applied on Gaussian filter output and considered only LL band for further processing to detect object/face. The modified background subtraction technique is applied on LL bands of input images. The adaptive threshold is computed using LL-band of reference image and object is detected through modified background subtraction. The detected object is passed through Gaussian filter to get final good quality object. The face detection is also identified using matching unit along with object detection unit. The reference image is replaced by face database images in the face detection. It is observed that the performance parameters such as TSR, FRR, FAR and hardware related results are improved compared to existing techniques.
The biometrics are used to identify a person effectively. In this paper, we propose optimised Face recognition system based on log transformation and combination of face image features vectors. The face images are preprocessed using Gaussian filter to enhance the quality of an image. The log transformation is applied on enhanced image to generate features. The feature vectors of many images of a single person image are converted into single vector using average arithmetic addition. The Euclidian distance(ED) is used to compare test image feature vector with database feature vectors to identify a person. It isexperimented that, the performance of proposed algorithm is better compared to existing algorithms.
The data transmission with information hiding is a challenging task in today world. To protect the secret data or image from attackers, the steganography techniques are essential. The steganography is a process of hiding the information from one channel to another in data communication. In this research work, Design of an Efficient Steganography Model using Lifting Based DWT and Modified-LSB Method on FPGA is proposed. The stegano module includes DWT (Discrete Wavelet Transformation) with lifting scheme for the cover image and encryption with Bit mapping for a secret image, an embedded module using Modified Least Significant Bit (MLSB) Method, and Inverse DWT to generate the stegano image. The recovery module includes DWT, decoding module with pixel extraction and bit retrievals, and decryption to generate the recovered secret image. The steganography model is designed using Verilog-HDL on Xilinx platform and implemented with Artix-7 Field Programmable Gate Array (FPGA). The hardware resource constraints like Area, time, and power utilization of the proposed model results are tabulated. The performance analysis of the work is evaluated using Peak Signal to Noise Ratio (PSNR) and Mean Square Error (MSE) Ratio for a different cover and secret images with better quality. The proposed steganography model operates at high speed, which improves communication performance.
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