In pulsed power systems, nanosecond switching transients are required to meet the demanding pulse specifications of voltage rise and fall times. To achieve these fast transients, SiC MOSFETs are promising semiconductor devices due to their high intrinsic switching speed. However, the parasitics of the semiconductor chip, the package and the board layout limit the achievable switching times. So far, no low inductive designs have been used to investigate the switching speed limits of SiC MOSFETs in pulsed power applications. Therefore, this paper focuses on the limits of the output voltage switching speed of a chopper type half bridge with an ohmic load, which is the fundamental switching cell of many solid-state pulse generators. The modelling of the half bridge is described and a linearized analytical model is presented for calculating the output voltage switching speed. For verification of the theoretical analysis, a sandwiched power module is built using a SiC MOSFET in a low inductive PCB-package.
Using GaN HEMTs in high current applications, such as pulsed power modulators for particle accelerator systems, requires the parallelization of multiple devices. In order to achieve a dynamically balanced current distribution between the parallel devices, synchronized gate voltages are crucial. Furthermore, the high switching speeds, which are often required in pulsed power systems, requires a high driving current capability and fast rise/fall times of the gate driver. Therefore, this paper presents a gate driver, based on a low voltage GaN HEMT half bridge, for driving four paralleled 650 V e-mode GaN HEMTs in a low inductive switching cell design.
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