This article describes the method of converting an analog signal into a digital code using a phase locked loop (PLL) circuit. The functional structure of the voltage-to-digital conversion circuit is considered. The application of the principle of phase-locked loop for controlling the duty cycle of the output signal of a phase detector when the voltage at the positive input of the operational amplifier included in the low-pass filter is investigated. In the modern world, analog-to-digital converters (ADCs) are available in almost every electronic device. The application of different ADC architectures is determined by their parameters and features by circuit and technological implementation. The phase-locked loop with a digital part (16-bit counter, storage register and data transfer interface) allows to obtain a precision analog-to-digital converter, based on a relatively simple circuit design, which has high accuracy and low noise level. Negative feedback of the PLL loop makes it possible to level the error of the passive elements of the low-pass filter (LPF) and the voltage controlled oscillator (VCO). The result of this work is an analysis of the ADC characteristics in the technological basis of 250 nm.
At the moment, almost any electronic product incorporates measuring sensors for converting physical quantities. These devices produce a signal of measurement information in a form suitable for transmission and further conversion. As a rule, the output signal from the measurement sensors undergoes first preprocessing such as amplification, filtering, modulation, etc. After preprocessing the prepared signal, various architectures of analog‑to‑digital converters (ADC) are used. The choice of ADC depends on the parameters of the conversion signal and the dynamic characteristics of the sensors used. This paper considers converting a square‑amplitude modulated signal from a current sensor to a pulse width using a phase‑locked loop (PLL). The architecture of the ADC based on the PLL circuit allows obtaining a linear dependence of the output signal duty cycle on the value of the measured input current. The layout of the device is implemented on a printed circuit board, the main components of which are: current sensor, which is a bridge circuit of magnetoresistive conductors; phase‑sensitive rectifier and microcircuit of a two‑channel PLL circuit made inTechnological Center.
The phase‑locked loop (PLL) is an integral part of many electronic products in modern electronics and radio engineering, which is used to form and process analog and digital signals. One of the non‑standard applications of the PLL circuit is to implement an analog voltage‑to‑pulse converter. This application of the PLL circuit allows you to create an analog‑to‑digital converter (ADC) with high resolution, and the implementation features of the PLL circuit can provide a number of advantages, such as high noise immunity, compensation for the errors of passive elements, operation in a wide temperature range, etc. The accuracy of the conversion in such a device depends on both the separately designed blocks of the PLL circuit and the parameters of the system as a whole. The paper discusses the implementation of a digital frequency‑phase detector (FFD) operating in the range from 0 to 2p. The basis of his work is the method of frequency‑phase detection, which reduces the time of transients in the PLL circuit, and also eliminates the detection of coherent and multiple frequencies of the reference signal.
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